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參數(shù)資料
| 型號(hào)： | XC4013XL-09PQ208C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 217 MHz, PQFP208 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 64K |
| 代理商： | XC4013XL-09PQ208C |
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R
DS005 (v. 1.7) October 4, 1999 - Product Specication
6-75
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000XL A.C. Characteristics
Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB ip-ops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the
static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Global Low Skew Buffer to Clock K
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Delay from pad through GLS buffer to
any clock input, K
TGLS
XC4002XL
0.3
2.1
1.8
1.6
1.5
ns
XC4005XL
0.4
2.7
2.3
2.0
1.9
ns
XC4010XL
0.5
3.2
2.8
2.4
2.3
ns
XC4013XL
0.6
3.6
3.1
2.7
2.6
2.3
ns
XC4020XL
0.7
4.0
3.5
3.0
2.9
ns
XC4028XL
0.9
4.4
3.8
33
3.2
ns
XC4036XL
1.1
4.8
4.2
3.6
3.5
3.1
ns
XC4044XL
1.2
5.3
4.6
4.0
3.9
ns
XC4052XL
1.3
5.7
5.0
4.5
4.4
ns
XC4062XL
1.4
6.3
5.4
4.7
4.6
4.0
ns
XC4085XL
1.6
7.2
6.2
5.7
5.5
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013XL-09PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013XL-09PQ208M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013XL-09PQ240C | 功能描述:IC FPGA C-TEMP 3.3V 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013XL-09PQ240C0314 | 制造商:Xilinx 功能描述: |
| XC4013XL-09PQ240C0624 | 制造商:Xilinx 功能描述: |
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