參數(shù)資料
型號(hào): XC4013E-4HQ240I
廠商: Xilinx Inc
文件頁(yè)數(shù): 50/68頁(yè)
文件大?。?/td> 0K
描述: IC FPGA I-TEMP 5V 4SPD 240-HQFP
產(chǎn)品變化通告: XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 24
系列: XC4000E/X
LAB/CLB數(shù): 576
邏輯元件/單元數(shù): 1368
RAM 位總計(jì): 18432
輸入/輸出數(shù): 192
門(mén)數(shù): 13000
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-58
May 14, 1999 (Version 1.6)
Table 22: Pin Functions During Conguration
CONFIGURATION MODE <M2:M1:M0>
SLAVE
SERIAL
<1:1:1>
MASTER
SERIAL
<0:0:0>
SYNCH.
PERIPHERAL
<0:1:1>
ASYNCH.
PERIPHERAL
<1:0:1>
MASTER
PARALLEL DOWN
<1:1:0>
MASTER
PARALLEL UP
<1:0:0>
USER
OPERATION
M2(HIGH) (I)
M2(LOW) (I)
M2(HIGH) (I)
(I)
M1(HIGH) (I)
M1(LOW) (I)
M1(HIGH) (I)
M1(LOW) (I)
M1(HIGH) (I)
M1(LOW) (I)
(O)
M0(HIGH) (I)
M0(LOW) (I)
M0(HIGH) (I)
M0(LOW) (I)
(I)
HDC (HIGH)
I/O
LDC (LOW)
I/O
INIT
I/O
DONE
PROGRAM (I)
PROGRAM
CCLK (I)
CCLK (O)
CCLK (I)
CCLK (O)
CCLK (I)
RDY/BUSY (O)
RCLK (O)
I/O
RS (I)
I/O
CS0 (I)
I/O
DATA 7 (I)
I/O
DATA 6 (I)
I/O
DATA 5 (I)
I/O
DATA 4 (I)
I/O
DATA 3 (I)
I/O
DATA 2 (I)
I/O
DATA 1 (I)
I/O
DIN (I)
DATA 0 (I)
I/O
DOUT
SGCK4-GCK6-I/O
TDI
TDI-I/O
TCK
TCK-I/O
TMS
TMS-I/O
TDO
TDO-(O)
WS (I)
A0
I/O
A1
PGCK4-GCK7-I/O
CS1
A2
I/O
A3
I/O
A4
I/O
A5
I/O
A6
I/O
A7
I/O
A8
I/O
A9
I/O
A10
I/O
A11
I/O
A12
I/O
A13
I/O
A14
I/O
A15
SGCK1-GCK8-I/O
A16
PGCK1-GCK1-I/O
A17
I/O
A18*
I/O
A19*
I/O
A20*
I/O
A21*
I/O
ALL OTHERS
Product Obsolete or Under Obsolescence
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