參數(shù)資料
型號(hào)： XC4013E-2BG225I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 56/68頁(yè)
文件大小： 0K
描述： IC FPGA I-TEMP 5V 2SPD 225-PBGA
產(chǎn)品變化通告： Product Discontinuation 28/Jul/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 192
門數(shù)： 13000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 225-BBGA
供應(yīng)商設(shè)備封裝： 225-PBGA
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-10
May 14, 1999 (Version 1.6)
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two ip-ops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type ip-ops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 2.
Latches (XC4000X only)
The CLB storage elements can also be congured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 2.
Clock Input
Each ip-op can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
F'
S/R
CONTROL
D
EC
RD
Bypass
SD
YQ
XQ
Q
S/R
CONTROL
D
EC
RD
SD
Q
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1
SR/H0
EC
X6692
C1 C4
4
Figure 1: Simplied Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode
K
EC
SR
D
Q
Power-Up or
GSR
XXXX
SR
Flip-Flop
XX
1
X
SR
__/
1*
0*
D
0X
0*
X
Q
Latch
11*
0*
X
Q
01*
0*
D
Both
X
0
0*
X
Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC4013E-2BG225C IC FPGA C-TEMP 5V 2SPD 225-PBGA
485897-2 CONN PLUG 4POS HOUSING W/DETENT
1-487769-3 015 HOUSING FFC RCPT 100CL SR
IDT71V546XS100PFG IC SRAM 4MBIT 100MHZ 100TQFP
487769-4 CONN RECEPT 6 POS .100 SLIMLINE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4013E-2BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2BG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2BG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2CB240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
XC4013E-2CB240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*