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參數(shù)資料
| 型號： | XC4008E-4PQ208I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | High Insulation Power Relay (Sealed 1 Form C 1-Coil Latch) |
| 中文描述： | FPGA, 324 CLBS, 6000 GATES, 111 MHz, PQFP208 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 75K |
| 代理商： | XC4008E-4PQ208I |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-112
February 11, 2000 (Version 1.8)
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data,
reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Device
Global Clock to Output
(fast) using OFF
TICKOF
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.5
14.0
14.5
15.0
16.0
16.5
17.0
10.2
10.7
10.8
10.9
11.0
12.6
8.7
9.1
9.2
9.3
9.4
10.2
10.8
5.8
6.2
6.4
6.6
6.8
7.2
7.4
–
ns
Global Clock to Output
(slew-limited) using OFF
TICKO
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
16.5
18.0
18.5
19.0
20.0
20.5
21.0
14.0
14.7
14.8
14.9
15.0
15.1
15.3
11.5
12.0
12.1
12.2
12.8
13.0
7.8
8.2
8.4
8.6
8.8
9.2
9.4
–
ns
Input Setup Time, using IFF
(no delay)
TPSUF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
2.5
2.0
1.9
1.4
1.0
0.5
0
2.3
1.2
1.0
0.6
0.2
0
2.3
1.2
1.0
0.6
0.2
0
1.5
0.8
0.6
0.2
0
–
ns
Input Hold Time, using IFF
(no delay)
TPHF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
4.6
5.0
6.0
7.0
7.5
8.0
4.0
4.5
4.7
5.1
5.5
6.5
6.7
7.0
4.0
4.5
4.7
5.1
5.5
5.7
5.9
1.5
2.0
2.5
3.0
3.5
–
ns
Input Setup Time, using IFF
(with delay)
TPSU
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
8.5
9.5
7.0
7.6
6.0
6.8
5.0
–
ns
Input Hold Time, using IFF
(with delay)
TPH
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
0
–
ns
OFF = Output Flip-Flop, IFF = Input Flip-Flop or Latch
OFF
Global Clock-to-Output Delay
.
X3202
TPG
OFF
Global Clock-to-Output Delay
.
X3202
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
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