參數(shù)資料
型號： XC4005XL-3VQ100I
廠商： Xilinx Inc
文件頁數(shù)： 33/68頁
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 3.3V 3SP 100VQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標準包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計： 6272
輸入/輸出數(shù)： 77
門數(shù)： 5000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
R
May 14, 1999 (Version 1.6)
6-43
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 41 on page 44 is a diagram of the XC4000 Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
XC4000 Series devices can also be congured through the
boundary scan logic. See “Readback” on page 55.
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-State Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single ip-op
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specied using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two
corresponding
pins
(BSCAN.TDO1
and
BSCAN.TDO2) allow user scan data to be shifted out on
TDO. The data register clock (BSCAN.DRCK) is available
for control of test logic which the user may wish to imple-
ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
is also provided (BSCAN.IDLE).
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
D
EC
Q
M
QL
rd
M
DELAY
M M
Input Clock IK
I - capture
I - update
GLOBAL
S/R
FLIP-FLOP/LATCH
INVERT
S/R
Input Data 1 I1
Input Data 2 I2
X5792
PAD
VCC
SLEW
RATE
PULL
UP
M
OUT
SEL
D
EC
Q
rd
M
INVERT
OUTPUT
M
INVERT
S/R
Ouput Clock OK
Clock Enable
Ouput Data O
O - update
Q - capture
O - capture
Boundary
Scan
M
EXTEST
TS - update
TS - capture
3-State TS
sd
TS INV
OUTPUT
TS/OE
PULL
DOWN
INPUT
Boundary
Scan
Boundary
Scan
Product Obsolete or Under Obsolescence
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