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參數(shù)資料
| 型號(hào)： | XC4002A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 97K |
| 代理商： | XC4002A |
2-77
P
4.0
4.0
Speed Grade
-6
-5
-4
Description
Symbol
Min Max
Min
Max
Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H' to X/Y outputs
C inputs via H' to X/Y outputs
T
ILO
T
IHO
T
HHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0
6.0
4.5
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1,F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators.
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
T
CKO
5.0
3.0
3.0
ns
Set-up Time before Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F'/G'
C
IN
input via F'/G' and H'
T
ICK
T
IHCK
T
HHCK
T
DICK
T
ECCK
T
RCK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
10.0
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
T
CKI
T
CKIH
T
CKHH
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time
T
CH
T
CL
5.0
5.0
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
RPW
T
RIO
5.0
4.0
4.0
ns
ns
9.0
8.0
7.0
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
T
MRW
T
MRQ
21.0
18.0
18.0
ns
ns
33.0
31.0
28.0
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
* Timing is based on the XC4005. For other devices see XACT timing calculator.
XC4003A
XC4005A
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| XC4005-36XL | XC4000XL Electrical Specifications |
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| XC4002A-6PC84C | 制造商:Xilinx 功能描述: |
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