Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
146
TQ144 Footprint
X-Ref Target - Figure 46
Figure 46: TQ144 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
51
I/O: Unrestricted, general-purpose user I/O
12
DUAL: Configuration pin, then possible
user I/O
12
VREF: User I/O or input voltage reference for
bank
14
DCI: User I/O or reference resistor input for
bank
8
GCLK: User I/O or global clock buffer
input
12
VCCO: Output voltage supply for bank
7
CONFIG: Dedicated configuration pins
4
JTAG: Dedicated JTAG port pins
4
VCCINT: Internal core voltage supply (+1.2V)
0
N.C.: No unconnected pins in this package
16
GND: Ground
4
VCCAUX: Auxiliary voltage supply (+2.5V)
IO
TD
I
PROG_
B
HS
W
AP_EN
IO
_L01N_0/
VRP_
0
IO
_L01P_0/
VRN_
0
GN
D
VCCO_TOP
IO
_L27N_0
GN
D
IO
_L27P_0
VCCAUX
VCCINT
IO
_L30N_0
IO
_L30P_0
IO
_L31N_0
IO
_L31P_0/
VREF_0
IO
_L32N_0
/G
C
LK
7
IO
_L32P_0
/G
C
LK
6
VCCO_TOP
IO
_L32N_1
/G
C
LK
5
IO
_L32P_1
/G
C
LK
4
IO
_L31N_1/
VREF_1
IO
_L31P_1
VCCINT
VCCAUX
IO
_L28N_
1
IO
_L28P_
1
GN
D
IO
VCCO_TOP
GN
D
IO
_L01N_1/
VRP_
1
IO
_L01P_1/
VRN_
1
TM
S
TC
K
TD
O
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
IO_L01P_7/VRN_7
1
108
IO_L01N_2/VRP_2
IO_L01N_7/VRP_7
2
107
IO_L01P_2/VRN_2
VCCO_LEFT
3
X
106
VCCO_RIGHT
IO/VREF_7
4
105
IO_L20N_2
IO_L20P_7
5
104
IO_L20P_2
IO_L20N_7
6
103
IO_L21N_2
IO_L21P_7
7
102
IO_L21P_2
IO_L21N_7
8
101
GND
GN D
9
100
IO_L22N_2
IO_L22P_7
10
99
IO_L22P_2
IO_L22N_7
11
98
IO_L23N_2/VREF_2
IO_L23P_7
12
97
IO_L23P_2
IO_L23N_7
13
96
IO_L24N_2
IO_L24P_7
14
95
IO_L24P_2
IO_L24N_7
15
94
GND
GN D
16
93
IO_L40N_2
IO_L40P_7
17
92
IO_L40P_2/VREF_2
IO_L40N_7/VREF_7
18
91
VCCO_RIGHT
VCCO_LEFT
19
90
IO_L40N_3/VREF_3
IO_L40P_6/VREF_6
20
8
9
IO_L40P_3
IO_L40N_6
21
88
GND
GN D
22
8
7
IO_L24N_3
IO_L24P_6
23
8
6
IO_L24P_3
IO_L24N_6/VREF_6
24
8
5
IO_L23N_3
IO_L23P_6
25
8
4
IO_L23P_3/VREF_3
IO_L23N_6
26
8
3
IO_L22N_3
IO_L22P_6
27
8
2
IO_L22P_3
IO_L22N_6
28
81
GND
GN D
29
8
0
IO_L21N_3
IO_L21P_6
30
79
IO_L21P_3
IO_L21N_6
31
78
IO_L20N_3
IO_L20P_6
32
77
IO_L20P_3
IO_L20N_6
33
76
IO
VCCO_LEFT
34
75
VCCO_RIGHT
IO_L01P_6/VRN_6
35
74
IO_L01N_3/VRP_3
IO_L01N_6/VRP_6
36
73
IO_L01P_3/VRN_3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
M1
M0
M2
IO
_L01P_5/
CS_B
_L01N_5/
RD
W
R_
B
GN
D
VCCO_BOTTOM
IO/VREF_
5
GN
D
IO
_L28P_5/
D7
IO
_L28N_5/
D6
VCCAUX
VCCINT
IO
_L31P_5/
D5
IO
_L31N_5/
D4
IO
_L32P_5
/G
C
LK
2
IO
_L32N_5
/G
C
LK
3
VCCO_BOTTO
M
IO
_L32P_4
/G
C
LK
0
IO
_L32N_4
/G
C
LK
1
IO_L31P_4/DOUT/BUSY
IO
_L31N_4
/INIT
_
B
IO
_L30P_4/
D3
IO
_L30N_4/
D2
VCCINT
VCCAUX
IO
_L27P_4/
D1
GN
D
IO
_L27N_4/
DIN/D0
VCCO_BOTTO
M
GN
D
IO
_L01P_4/
VRN_
4
IO
_L01N_4/
VRP_
4
IO/VREF_
4
DONE
CCL
K
Bank 5
(no DCI)
Bank
3
Bank
2
VCCO for
Top Edge
VCCO
for
Right
Edge
VCCO for Bottom Edge
Bank 0
Bank 1
Bank
7
Bank 4
Bank
6
VCCO
for
Left
Edge
DS099-4_08_121103