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參數(shù)資料
| 型號： | XC3S400-4FGG456I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 206/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 400K STD 456FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 60 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 896 |
| 邏輯元件/單元數(shù)： | 8064 |
| RAM 位總計： | 294912 |
| 輸入/輸出數(shù)： | 264 |
| 門數(shù)： | 400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 456-BBGA |
| 供應(yīng)商設(shè)備封裝： | 456-FBGA |
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Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
39
DFS Clock Output Connections
There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illustrated
in sections [a] and [c], respectively, of Figure 21. This is similar to what has already been described for the DLL component.
In the on-chip case, it is possible to connect either of the DFS’s two output clock signals through general routing resources
to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock
network. The optional feedback loop is formed in this way, routing CLK0 to a global clock net, which in turn drives the CLKFB
input.
In the off-chip case, the DFS’s two output clock signals, plus CLK0 for an optional feedback loop, can exit the FPGA using
output buffers (OBUF) to drive a clock network plus registers on the board. The feedback loop is formed by feeding the CLK0
signal back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global
clock net is connected directly to the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase of a DCM clock output signal relative to the CLKIN signal: First,
there are nine clock outputs that employ the DLL to achieve a desired phase relationship: CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKDV CLKFX, and CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in this section to provide a still finer degree of control. The PS
component is only available when the DLL is operating in its low-frequency mode. The PS component phase shifts the DCM
output clocks by introducing a "fine phase shift" (TPS) between the CLKFB and CLKIN signals inside the DLL component.
The user can control this fine phase shift down to a resolution of 1/256 of a CLKIN cycle or one tap delay (DCM_TAP),
whichever is greater. When in use, the PS component shifts the phase of all nine DCM clock output signals together. If the
PS component is used together with a DCM clock output such as the CLK90, CLK180, CLK270, CLK2X180 and CLKFX180,
then the fine phase shift of the former gets added to the coarse phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS component for use in addition to selecting between two operating
modes. As described in Table 20, this attribute has three possible values: NONE, FIXED and VARIABLE. When
CLKOUT_PHASE_SHIFT is set to NONE, the PS component is disabled and its inputs, PSEN, PSCLK, and PSINCDEC,
must be tied to GND. The set of waveforms in section [a] of Figure 22 shows the disabled case, where the DLL maintains a
zero-phase alignment of signals CLKFB and CLKIN upon which the PS component has no effect. The PS component is
enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase mode and the
Variable Phase mode, respectively. These two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to CLKIN by setting and/or adjusting the value of the PHASE_SHIFT
attribute. This value must be an integer ranging from –255 to +255. The PS component uses this value to calculate the
desired fine phase shift (TPS) as a fraction of the CLKIN period (TCLKIN). Given values for PHASE-SHIFT and TCLKIN, it is
possible to calculate TPS as follows:
TPS = TCLKIN(PHASE_SHIFT/256)
Equation 4
Both the Fixed Phase and Variable Phase operating modes employ this calculation. If the PHASE_SHIFT value is zero, then
CLKFB and CLKIN will be in phase, the same as when the PS component is disabled. When the PHASE_SHIFT value is
positive, the CLKFB signal will be shifted later in time with respect to CLKIN. If the attribute value is negative, the CLKFB
signal will be shifted earlier in time with respect to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of the TCLKIN, as determined by Equation 4 and its user-selected
PHASE_SHIFT value P. The set of waveforms insection [b] of Figure 22 illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK and PSINCDEC inputs are not used and
must be tied to GND. Fixed phase shift requires ISE software version 10.1.03 or later.
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| XC3S400-5FGG456C | SPARTAN-3A FPGA 400K 456-FBGA |
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| XC2V40-4FG256I | IC FPGA VIRTEX-II 256FGBGA |
| XC2V40-5FGG256C | IC FPGA VIRTEX-II 40K 256-FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S400-4FT256C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 630MHZ 1.2V 256FTBGA - Trays |
| XC3S400-4FT256C0954 | 制造商:Xilinx 功能描述: |
| XC3S400-4FT256I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 630MHZ 1.2V 256FTBGA - Trays |
| XC3S400-4FTG256C | 功能描述:IC SPARTAN-3 FPGA 400K 256-FTBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3S400-4FTG256I | 功能描述:SPARTAN3A FPGA 400K STD 256FTBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
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