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| 型號(hào)： | XC3S1000-4PQ208C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 29/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-4PQ208C |
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Spartan-3 FPGA Family: Functional Description
22
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
DLL Clock Input Connections
An external clock source enters the FPGA using a Global
Clock Input Buffer (IBUFG), which directly accesses the glo-
bal clock network or an Input Buffer (IBUF). Clock signals
within the FPGA drive a global clock net using a Global
Clock Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and exter-
nal connections are shown in
Figure 15a
and
Figure 15c
,
respectively. A differential clock (e.g., LVDS) can serve as
an input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simulta-
neously drive the four BUFGMUX buffers on the same die
edge (top or bottom). All DCM clock outputs can simulta-
neously drive general routing resources, including intercon-
nect leading to OBUF buffers.
The feedback loop is essential for DLL operation and is
established by driving the CLKFB input with either the CLK0
or the CLK2X signal so that any undesirable clock distribu-
tion delay is included in the loop. It is possible to use either
of these two signals for synchronizing any of the seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The value assigned to the CLK_FEEDBACK
attribute must agree with the physical feedback connection:
a value of 1X for the CLK0 case, 2X for the CLK2X case. If
the DCM is used in an application that does not require the
DLL — i.e., only the DFS is used — then there is no feed-
back loop so CLK_FEEDBACK is set to NONE.
There are two basic cases that determine how to connect
the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are
illustrated in
Figure 15a
through
Figure 15d
.
Table 13:
DLL Attributes
Attribute
Description
Values
CLK_FEEDBACK
Chooses either the CLK0 or CLK2X output to drive the
CLKFB input
NONE, 1X, 2X
DLL_FREQUENCY_MODE
Chooses between High Frequency and Low
Frequency modes
LOW, HIGH
CLKIN_DIVIDE_BY_2
Halves the frequency of the CLKIN signal just as it
enters the DCM
TRUE, FALSE
CLKDV_DIVIDE
Selects constant used to divide the CLKIN input
frequency to generate the CLKDV output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5,
6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11,
12, 13, 14, 15, and 16.
DUTY_CYCLE_CORRECTION
Enables 50% duty cycle correction for the CLK0,
CLK90, CLK180, and CLK270 outputs
TRUE, FALSE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4PQ208I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4TQ144I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4TQG144C | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4PQG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
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