參數(shù)資料
型號(hào)： XC3164A-3PC84C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 16/76頁(yè)
文件大小： 0K
描述： IC LOGIC CL ARRAY 6400GAT 84PLCC
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 15
系列： XC3000A/L
LAB/CLB數(shù)： 224
RAM 位總計(jì)： 46064
輸入/輸出數(shù)： 70
門(mén)數(shù)： 4500
電源電壓： 4.25 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線(xiàn)）
供應(yīng)商設(shè)備封裝： 84-PLCC
其它名稱(chēng)： 122-1045
R
November 9, 1998 (Version 3.1)
7-25
XC3000 Series Field Programmable Gate Arrays
7
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
X5989_01
CE
GENERAL-
PURPOSE
USER I/O
PINS
M0
M1
PWRDWN
DOUT
M2
HDC
OTHER
I/O PINS
RESET
DIN
CCLK
DATA
CLK
+5 V
OE/RESET
XC3000
FPGA
DEVICE
D/P
SCP
CEO
CASCADED
SERIAL
MEMORY
LDC
INIT
XC17xx
RESET
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
DURING CONFIGURATION
THE 5 k
M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
(LOW RESETS THE XC17xx ADDRESS POINTER)
TO CCLK OF OPTIONAL
VCC
VPP
+5 V
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN
SERIES WITH M1
*
CE
DATA
CLK
OE/RESET
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
INIT
+5V
Figure 23: Master Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
AMC36DRYN-S13 CONN EDGECARD 72POS .100 EXTEND
XC3142A-3PQ100C IC LOGIC CL ARRAY 4200GAT 100PQF
AMC36DRYH-S13 CONN EDGECARD 72POS .100 EXTEND
XC3130A-3PQ100C IC LOGIC CL ARRAY 3000GAT 100PQF
XC3130A-3PC84C IC LOGIC CL ARRAY 3000GAT 84PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3164A-3PC84I 制造商:Xilinx 功能描述:
XC3164A-3PQ160C 制造商:Xilinx 功能描述:
XC3164A-3PQ160I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3164A-3TQ144C 功能描述:IC FPGA 224 CLB'S 144-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3164A-3TQ144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*