參數(shù)資料
型號(hào)： XC3020A7PC68I
廠商： Xilinx, Inc.
英文描述： IC-SMD-FPGA
中文描述： 集成電路貼片的FPGA
文件頁(yè)數(shù)： 76/76頁(yè)
文件大?。?/td> 731K
代理商： XC3020A7PC68I
R
November 9, 1998 (Version 3.1)
7-11
XC3000 Series Field Programmable Gate Arrays
7
General Purpose Interconnect
General purpose interconnect, as shown in Figure 10, con-
sists of a grid of five horizontal and five vertical metal seg-
ments located between the rows and columns of logic and
IOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow programmed interconnections between the metal grid
segments of adjoining rows and columns. The switches of
an unprogrammed device are all non-conducting. The con-
nections through the switch matrix may be established by
the automatic routing or by selecting the desired pairs of
matrix pins to be connected or disconnected. The legiti-
mate switching matrix combinations for each pin are indi-
cated in Figure 11.
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices, above
and to the right. The other PIPs adjacent to the matrices
are accessed to or from Longlines. The development sys-
tem automatically defines the buffer direction based on the
location of the interconnection network source. The delay
calculator of the development system automatically calcu-
lates and displays the block, interconnect and buffer delays
for any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided.
Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct inter-
connect to drive the D input of the block immediately above
and the A input of the block below. Direct interconnect
should be used to maximize the speed of high-performance
portions of logic. Where logic blocks are adjacent to IOBs,
direct connect is provided alternately to the IOB inputs (I)
and outputs (O) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent IOBs. Direct interconnections of IOBs with CLBs
are shown in Figure 13.
D
Q
D
Q
D
Q
Count Enable
Parallel Enable
Clock
D2
D1
D0
Dual Function of 4 Variables
Function of 6 Variables
Function of 5 Variables
Q2
Q1
Q0
FG
Mode
F
Mode
FGM
Mode
Terminal
Count
X5383
Figure 7: Counter.
The modulo-8 binary counter with parallel enable and
clock enable uses one combinatorial logic block of each
option.
Figure 8: A Design Editor view of routing resources
used to form a typical interconnection network from
CLB GA.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3020A-7PC68I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3020A-7PC84C 功能描述:IC LOGIC CL ARRAY 2000GAT 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3020A-7PC84C0100 制造商:Xilinx 功能描述:
XC3020A-7PC84I 制造商:Xilinx 功能描述:
XC3020A-7PCG68C 制造商:Xilinx 功能描述:
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