參數(shù)資料
型號: XC3020A7PC68I
廠商: Xilinx, Inc.
英文描述: IC-SMD-FPGA
中文描述: 集成電路貼片的FPGA
文件頁數(shù): 22/76頁
文件大?。?/td> 731K
代理商: XC3020A7PC68I
R
November 9, 1998 (Version 3.1)
7-31
XC3000 Series Field Programmable Gate Arrays
7
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
RESET
X5993
FPGA
General-
Purpose
User I/O
Pins
+5 V
M0
M1
PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
...
Other
I/O Pins
INIT
+5 V
5 k
If Readback is
Activated, a
5-k
Resistor is
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
Figure 29: Slave Serial Mode Circuit Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3020A-7PC68I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3020A-7PC84C 功能描述:IC LOGIC CL ARRAY 2000GAT 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
XC3020A-7PC84C0100 制造商:Xilinx 功能描述:
XC3020A-7PC84I 制造商:Xilinx 功能描述:
XC3020A-7PCG68C 制造商:Xilinx 功能描述: