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參數(shù)資料
| 型號(hào)： | XC3000ASERIES |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大小： | 731K |
| 代理商： | XC3000ASERIES |
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R
November 9, 1998 (Version 3.1)
7-59
XC3000 Series Field Programmable Gate Arrays
7
XC3100L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100L Operating Conditions
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right
to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V.
Operating conditions are guaranteed in the 3.0 – 3.6 V VCC range.
XC3100L DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA
configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not
exceed 100 mA per VCC pin. The number of ground pins varies from the XC3142L to the XC3190L.
3. Not tested. Allows undriven pins to float High. For any other purpose, use an external pull-up.
Symbol
Description
Min
Max
Units
VCC
Supply voltage relative to GND Commercial 0
°C to +85°C junction
3.0
3.6
V
VIH
High-level input voltage
2.0
VCC + 0.3
V
VIL
Low-level input voltage
-0.3
0.8
V
TIN
Input signal transition time
250
ns
Symbol
Description
Min
Max
Units
VOH
High-level output voltage (@ IOH = -4.0 mA, VCC min)
2.4
V
High-level output voltage (@ IOH = -100.0 A, VCC min)
VCC -0.2
V
VOL
Low-level output voltage (@ IOH = 4.0 mA, VCC min)
0.40
V
Low-level output voltage (@ IOH = +100.0 A, VCC min)
0.2
V
VCCPD
Power-down supply voltage (PWRDWN must be Low)
2.30
V
ICCO
Quiescent FPGA supply current
Chip thresholds programmed as CMOS levels1
1.5
mA
IIL
Input Leakage Current
-10
+10
A
CIN
Input capacitance
(sample tested)
All pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
IRIN
Pad pull-up (when selected) @ VIN = 0 V
3
0.02
0.17
mA
IRLL
Horizontal long line pull-up (when selected) @ logic Low
0.20
2.80
mA
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相關(guān)代理商/技術(shù)參數(shù) |
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