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| 型號： | XC3000ASERIES |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 48/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3000ASERIES |
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R
XC3000 Series Field Programmable Gate Arrays
7-54
November 9, 1998 (Version 3.1)
XC3100A Absolute Maximum Ratings
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Note:
1. Timing is based on the XC3142A, for other devices see timing calculator.
The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A
devices.
Symbol
Description
Units
VCC
Supply voltage relative to GND
–0.5 to +7.0
V
VIN
Input voltage with respect to GND
–0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
–0.5 to VCC +0.5
V
TSTG
Storage temperature (ambient)
–65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
TJ
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
Speed Grade
-4-3-2-1
-09
Description
Symbol
Max
Units
Global and Alternate Clock Distribution1
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
6.5
5.1
5.6
4.3
4.7
3.7
4.3
3.5
3.9
3.1
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
(XC3100)
(XC3100A)
T
↓ to L.L. active and valid with single pull-up resistor
T
↓ to L.L. active and valid with pair of pull-up resistors
T
↑ to L.L. High with single pull-up resistor
T
↑ to L.L. High with pair of pull-up resistors
TIO
TON
TPUS
TPUF
3.7
3.6
5.0
6.5
13.5
10.5
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
2.1
3.1
4.6
8.9
5.9
ns
BIDI
Bidirectional buffer delay
TBIDI
1.2
1.0
0.9
0.85
0.75
ns
Prelim
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XC3000FM | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC3000L | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
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| XC3020 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC3020-100CB100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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