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參數(shù)資料
| 型號： | XC2V6000-5BFG957I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 260/318頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-II 957FCBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | Virtex®-II |
| LAB/CLB數(shù)： | 8448 |
| RAM 位總計： | 2654208 |
| 輸入/輸出數(shù)： | 684 |
| 門數(shù)： | 6000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 957-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 957-FCBGA（40x40） |
Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
38
ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Readback
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary-Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Platform FPGA User Guide.
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the VBATT pin, when the
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II Platform FPGA User Guide. For
devices that support this feature, please contact your sales
representative for specific ordering part number.
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
Revision History
This section records the change history for this module of the data sheet.
Date
Version
Revision
11/07/00
1.0
Early access draft.
12/06/00
1.1
Initial release.
01/15/01
1.2
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01
1.3
The data sheet was divided into four modules (per the current style standard). A note was
added to Table 1.
04/02/01
1.5
Under Input/Output Individual Options, the range of values for optional pull-up and
pull-down resistors was changed to 10 - 60 K
Ω from 50 - 100 KΩ.
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
07/30/01
1.6
Added Table 6
.
Changed definition of multiply and divide integer ranges under Digital Clock Manager
Made numerous minor edits throughout this module.
10/02/01
1.7
Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock
10/12/01
1.8
Made clarifying edits under Digital Clock Manager (DCM).
11/29/01
1.9
Changed bitstream lengths for each device in Table 26.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XC2V6000-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
| XC2V6000-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
| XC2V6000-5FF1152I | 功能描述:IC FPGA VIRTEX-II 1152FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC2V60005FF1517C | 制造商:Xilinx 功能描述: |
| XC2V6000-5FF1517I | 功能描述:IC FPGA VIRTEX-II 1517FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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