參數資料
| 型號： | XC2S200E-6PQ208I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 36/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 1176 CLB'S 208-PQFP |
| 標準包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數： | 1176 |
| 邏輯元件/單元數： | 5292 |
| RAM 位總計： | 57344 |
| 輸入/輸出數： | 146 |
| 門數： | 200000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | Q5479689 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
DS077-3 (v3.0) August 9, 2013
33
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Power-On Requirements
Spartan-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol
Description
Min(1)
Typ
Max
Units
ICCPO
Total VCCINT supply current
required during power-on
Commercial
XC2S50E - XC2S300E
After PCN(2)
300
-
mA
Before
PCN(2)
500
-
mA
XC2S400E - XC2S600E
500
-
mA
Industrial
XC2S50E - XC2S300E
After PCN(2)
500
-
mA
Before
PCN(2)
2
-
A
XC2S400E - XC2S600E
700
-
mA
TCCPO
VCCINT(3,4) ramp time
After PCN(2)
500
-
μs
Before PCN(2)
2
-
50
ms
IHSPO
AC current per pin during power-on in
hot-swap applications when
VIN > VCCO + 0.4V; duration < 10ns
After PCN(2)
-
±60
-
μA
Notes:
1.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2.
Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3.
The ramp time is measured from GND to 1.8V on a fully loaded board.
4.
VCCINT must not dip in the negative direction during power on.
5.
I/Os are not guaranteed to be disabled until VCCINT is applied.
6.
For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL(1)
–0.5
0.8
2.0
3.6
0.4
2.4
24
–24
LVCMOS2
–0.5
0.7
1.7
2.7
0.4
1.9
12
–12
LVCMOS18
–0.5
35% VCCO
65% VCCO
1.95
0.4
VCCO – 0.4
8
–8
PCI, 3.3V
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note (2)
GTL
–0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
-
40
-
GTL+
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
-
36
-
相關PDF資料 |
PDF描述 |
|---|---|
| 5205817-1 | CONN SCREWLOCK FEMALE 2 SETS/BAG |
| XC6SLX25-N3FTG256C | IC FPGA SPARTAN-6 256FBGA |
| XC2V40-5CSG144C | IC FPGA VIRTEX-II 40K 144-CSBGA |
| 5745563-1 | CONN D-SUB FEMALE SCREW LOCK |
| XC2V40-4CSG144I | IC FPGA VIRTEX-II 40K 144-CSBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S200E-6PQG208C | 功能描述:IC SPARTAN-IIE FPGA 200K 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-IIE 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC2S200E-6PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S200E-6TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S200E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S200E-6TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
發(fā)布緊急采購，3分鐘左右您將得到回復。