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參數(shù)資料
| 型號(hào)： | XC2S200E-6PQ208I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 13/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 1176 CLB'S 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 1176 |
| 邏輯元件/單元數(shù)： | 5292 |
| RAM 位總計(jì)： | 57344 |
| 輸入/輸出數(shù)： | 146 |
| 門數(shù)： | 200000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 其它名稱： | Q5479689 |
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12
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
is required for most output standards and for LVTTL,
LVCMOS, and PCI inputs.
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. About
one in six of the I/O pins in the bank assume this role.
VREF pins within a bank are interconnected internally and
consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. The VCCO and VREF pins for each bank appear in the
device pinout tables.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a superset of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All VREF pins for the largest device anticipated must
be connected to the VREF voltage, and not used for I/O.
on I/O resources.
Hot Swap, Hot Insertion, Hot Socketing Support
The I/O pins support hot swap — also called hot insertion
and hot socketing — and are considered CompactPCI
Friendly according to the PCI Bus v2.2 Specification. Con-
sequently, an unpowered Spartan-IIE FPGA can be
plugged directly into a powered system or backplane with-
out affecting or damaging the system or the FPGA. The hot
swap
functionality
is
built
into
every
XC2S150E,
XC2S400E, and XC2S600E device. All other Spartan-IIE
devices built after Product Change Notice PCN2002-05 also
include hot swap functionality.
To support hot swap, Spartan-IIE devices include the follow-
ing I/O features.
Signals can be applied to Spartan-IIE FPGA I/O pins
before powering the FPGA’s VCCINT or VCCO supply
inputs.
Spartan-IIE FPGA I/O pins are high-impedance (i.e.,
three-stated) before and throughout the power-up and
configuration processes when employing a
configuration mode that does not enable the
preconfiguration weak pull-up resistors (see Table 11,
There is no current path from the I/O pin back to the
VCCINT or VCCO voltage supplies.
Spartan-IIE FPGAs are immune to latch-up during hot
swap.
Once connected to the system, each pin adds a small
amount of capacitance (CIN). Likewise, each I/O consumes
a small amount of DC current, equivalent to the input leak-
age specification (IL). There also may be a small amount of
temporary AC current (IHSPO) when the pin input voltage
exceeds VCCO plus 0.4V, which lasts less than 10 ns.
A weak-keeper circuit within each user-I/O pin is enabled
during the last frame of configuration data and has no
noticeable effect on robust system signals driven by an
active driver or a strong pull-up or pull-down resistor.
Undriven or floating system signals may be affected. The
specific effect depends on how the I/O pin is configured.
User-I/O pins configured as outputs or enabled outputs
have a weak pull-up resistor to VCCO during the last config-
uration frame. User-I/O pins configured as inputs or bidirec-
tional I/Os have weak pull-down resistors. The weak-keeper
circuit turns off when the DONE pin goes High, provided
that it is not used in the configured application.
Table 4: Compatible Standards
VCCO
Compatible Standards
3.3V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
LVPECL, GTL, GTL+
2.5V
SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus
LVDS, GTL, GTL+
1.8V
LVCMOS18, GTL, GTL+
1.5V
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Table 5: I/O Banking
Package
TQ144, PQ208
FT256, FG456,
FG676
VCCO Banks
Interconnected as 1
8 independent
VREF Banks
8 independent
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S200E-6PQG208C | 功能描述:IC SPARTAN-IIE FPGA 200K 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S200E-6PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S200E-6TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S200E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S200E-6TQG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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