參數(shù)資料
型號： XC2S15-5CS144C
廠商： Xilinx Inc
文件頁數(shù)： 57/99頁
文件大?。?/td> 0K
描述： IC FPGA 2.5V C-TEMP 144-CSBGA
標(biāo)準(zhǔn)包裝： 198
系列： Spartan®-II
LAB/CLB數(shù)： 96
邏輯元件/單元數(shù)： 432
RAM 位總計： 16384
輸入/輸出數(shù)： 86
門數(shù)： 15000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-LCSBGA（12x12）
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
60
R
Calculation of TIOOP as a Function of
Capacitance
TIOOP is the propagation delay from the O Input of the IOB
to the pad. The values for TIOOP are based on the standard
capacitive load (CSL) for each I/O standard as listed in the
For other capacitive loads, use the formulas below to
calculate an adjusted propagation delay, TIOOP1.
TIOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL
Where:
Adj
is selected from "IOB Output Delay
according to the I/O standard used
CLOAD is the capacitive load for the design
FL
is the capacitance scaling factor
Delay Measurement Methodology
Standard
VL(1)
VH (1)
Meas.
Point
VREF
Typ(2)
LVTTL
0
3
1.4
-
LVCMOS2
0
2.5
1.125
-
PCI33_5
Per PCI Spec
-
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
VREF – 0.2 VREF + 0.2 VREF
0.80
GTL+
VREF – 0.2 VREF + 0.2 VREF
1.0
HSTL Class I
VREF – 0.5 VREF + 0.5 VREF
0.75
HSTL Class III
VREF – 0.5 VREF + 0.5 VREF
0.90
HSTL Class IV VREF – 0.5 VREF + 0.5 VREF
0.90
SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF
1.5
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF
1.25
CTT
VREF – 0.2 VREF + 0.2 VREF
1.5
AGP
VREF –
(0.2xVCCO)
VREF +
(0.2xVCCO)
VREF Per AGP
Spec
Notes:
1.
Input waveform switches between VL and VH.
2.
Measurements are made at VREF Typ, Maximum, and
Minimum. Worst-case values are reported.
3.
I/O parameter measurements are made with the capacitance
values shown in the table, "Constants for Calculating TIOOP".
See Xilinx application note XAPP179 for the appropriate
terminations.
4.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Constants for Calculating TIOOP
Standard
CSL(1)
(pF)
FL
(ns/pF)
LVTTL Fast Slew Rate, 2 mA drive
35
0.41
LVTTL Fast Slew Rate, 4 mA drive
35
0.20
LVTTL Fast Slew Rate, 6 mA drive
35
0.13
LVTTL Fast Slew Rate, 8 mA drive
35
0.079
LVTTL Fast Slew Rate, 12 mA drive
35
0.044
LVTTL Fast Slew Rate, 16 mA drive
35
0.043
LVTTL Fast Slew Rate, 24 mA drive
35
0.033
LVTTL Slow Slew Rate, 2 mA drive
35
0.41
LVTTL Slow Slew Rate, 4 mA drive
35
0.20
LVTTL Slow Slew Rate, 6 mA drive
35
0.100
LVTTL Slow Slew Rate, 8 mA drive
35
0.086
LVTTL Slow Slew Rate, 12 mA drive
35
0.058
LVTTL Slow Slew Rate, 16 mA drive
35
0.050
LVTTL Slow Slew Rate, 24 mA drive
35
0.048
LVCMOS2
35
0.041
PCI 33 MHz 5V
50
0.050
PCI 33 MHZ 3.3V
10
0.050
PCI 66 MHz 3.3V
10
0.033
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class I
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Notes:
1.
I/O parameter measurements are made with the capacitance
values shown above. See Xilinx application note XAPP179
for the appropriate terminations.
2.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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參數(shù)描述
XC2S15-5CS144I 功能描述:IC FPGA 2.5V I-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC2S15-5CSG144C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S15-5CSG144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S15-5FG256C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S15-5FG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
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