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參數(shù)資料
| 型號： | XC2S15-5CS144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 32/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 144-CSBGA |
| 標準包裝： | 198 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 96 |
| 邏輯元件/單元數(shù)： | 432 |
| RAM 位總計： | 16384 |
| 輸入/輸出數(shù)： | 86 |
| 門數(shù)： | 15000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-TFBGA，CSPBGA |
| 供應商設備封裝： | 144-LCSBGA（12x12） |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
38
R
PCI — Peripheral Component Interface
The Peripheral Component Interface (PCI) standard
specifies support for both 33 MHz and 66 MHz PCI bus
applications. It uses a LVTTL input buffer and a push-pull
output buffer. This standard does not require the use of a
reference voltage (VREF) or a board termination voltage
(VTT), however, it does require a 3.3V output source voltage
(VCCO). I/Os configured for the PCI, 33 MHz, 5V standard
are also 5V-tolerant.
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic (GTL) standard is a
high-speed bus standard (JESD8.3). Xilinx has
implemented the terminated variation of this standard. This
standard requires a differential amplifier input buffer and an
open-drain output buffer.
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus (GTL+) standard is a
high-speed bus standard (JESD8.3).
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic (HSTL) standard is a
general purpose high-speed, 1.5V bus standard (EIA/JESD
8-6). This standard has four variations or classes. Versatile
I/O devices support Class I, III, and IV. This standard
requires a Differential Amplifier input buffer and a Push-Pull
output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V (SSTL3)
standard is a general purpose 3.3V memory bus standard
(JESD8-8). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL3
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5V (SSTL2)
standard is a general purpose 2.5V memory bus standard
(JESD8-9). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL2
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
CTT — Center Tap Terminated
The Center Tap Terminated (CTT) standard is a 3.3V
memory bus standard (JESD8-4). This standard requires a
Differential Amplifier input buffer and a Push-Pull output
buffer.
AGP-2X — Advanced Graphics Port
The AGP standard is a 3.3V Advanced Graphics Port-2X
bus standard used with processors for graphics
applications. This standard requires a Push-Pull output
buffer and a Differential Amplifier input buffer.
Library Primitives
The Xilinx library includes an extensive list of primitives
designed to provide support for the variety of Versatile I/O
features. Most of these primitives represent variations of the
five generic Versatile I/O primitives:
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
These primitives are available with various extensions to
define the desired I/O standard. However, it is
recommended that customers use a a property or attribute
on the generic primitive to specify the I/O standard. See
IBUF
Signals used as inputs to the Spartan-II device must source
an input buffer (IBUF) via an external input port. The generic
IBUF primitive appears in Figure 35. The assumed standard
is LVTTL when the generic IBUF has no specified extension
or property.
When the IBUF primitive supports an I/O standard such as
LVTTL, LVCMOS, or PCI33_5, the IBUF automatically
configures as a 5V tolerant input buffer unless the VCCO for
the bank is less than 2V. If the single-ended IBUF is placed
in a bank with an HSTL standard (VCCO < 2V), the input
buffer is not 5V tolerant.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent VREF banks
internally. See Figure 36 for a representation of the I/O
banks. Within each bank approximately one of every six I/O
pins is automatically configured as a VREF input.
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same
standard. How to specify a specific location for the IBUF via
Figure 35: Input Buffer (IBUF) Primitive
O
I
IBUF
DS001_35_061200
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S15-5CS144I | 功能描述:IC FPGA 2.5V I-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC2S15-5CSG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-5CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-5FG256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-5FG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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