參數(shù)資料
型號(hào)： XC2S100-5FG256C
廠商： Xilinx Inc
文件頁數(shù)： 36/99頁
文件大?。?/td> 0K
描述： IC FPGA 2.5V 600 CLB'S 256-FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 176
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
其它名稱： 122-1226
XC2S100-5FG256C-ND
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
41
R
IOBUF_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
When the IOBUF primitive supports an I/O standard such
as LVTTL, LVCMOS, or PCI33_5, the IBUF automatically
configures as a 5V tolerant input buffer unless the VCCO for
the bank is less than 2V. If the single-ended IBUF is placed
in a bank with an HSTL standard (VCCO < 2V), the input
buffer is not 5V tolerant.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent VREF banks
internally. See Figure 36, page 39 for a representation of
the Spartan-II FPGA I/O banks. Within each bank
approximately one of every six I/O pins is automatically
configured as a VREF input.
Additional restrictions on the Versatile I/O IOBUF
placement require that within a given VCCO bank each
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require VCCO can be placed within the same VCCO bank.
The LOC property can specify a location for the IOBUF.
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal,
activate the delay element with the DELAY=TRUE property.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate primitive to the output net of the IOBUF
(PULLUP, PULLDOWN, or KEEPER).
Versatile I/O Properties
Access to some of the Versatile I/O features (for example,
location constraints, input delay, output drive strength, and
slew rate) is available through properties associated with
these features.
Input Delay Properties
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to
override this default.
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to
provide higher performance. To delay the input signal,
activate the delay element with the DELAY=TRUE property.
IOB Flip-Flop/Latch Property
The I/O Block (IOB) includes an optional register on the
input path, an optional register on the output path, and an
optional register on the 3-state control pin. The design
implementation software automatically takes advantage of
these registers when the following option for the Map
program is specified:
map -pr b <filename>
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each Versatile I/O primitive with the
location constraint LOC attached to the Versatile I/O
primitive. The external port identifier indicates the value of
the location constrain. The format of the port identifier
depends on the package chosen for the specific design.
The LOC properties use the following form:
LOC=A42
LOC=P37
Output Slew Rate Property
In the case of the LVTTL output buffers (OBUF, OBUFT, and
IOBUF), slew rate control can be programmed with the
SLEW= property. By default, the slew rate for each output
buffer is reduced to minimize power bus transients when
switching non-critical signals. The SLEW= property has one
of the two following values.
SLEW=SLOW
SLEW=FAST
Output Drive Strength Property
For the LVTTL output buffers (OBUF, OBUFT, and IOBUF,
the desired drive strength can be specified with the DRIVE=
Figure 40: Input/Output Buffer Primitiveprimitive
(IOBUF)
IO
I
IOBUF
DS001_40_061200
T
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S1005-FG256C 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 2700 Cell, 256 Pin, Plastic, BGA
XC2S1005FG256I 制造商:XILINX 功能描述:New
XC2S100-5FG256I 功能描述:IC FPGA 2.5V I-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S1005FG456C 制造商:Xilinx 功能描述:
XC2S100-5FG456C 功能描述:IC FPGA 2.5V 600 CLB'S 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
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