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參數(shù)資料
| 型號： | XA6SLX9-3CSG324Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN 6 324CSGBGA |
| 標準包裝： | 126 |
| 系列： | Spartan®-6 LX XA |
| LAB/CLB數(shù)： | 715 |
| 邏輯元件/單元數(shù)： | 9152 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 200 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-LFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 324-CSPBGA |
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012
Product Specification
5
Clock Distribution
Each XA Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short
propagation delay, and extremely low skew.
Global Clock Lines
In each XA Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock
lines must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable
function. Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.
I/O Clocks
I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer
(SERDES) circuits, as described in the I/O Logic section.
Block RAM
Every XA Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two
completely independent ports that share only the stored data.
Synchronous Operation
Each memory access, whether read or write, is controlled by the clock. All inputs, data, address, clock enables, and write
enables are registered. The data output is always latched, retaining data until the next operation. An optional output data
pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation in dual-port mode, the data output can reflect either the previously stored data, the newly written
data, or remain unchanged.
Programmable Data Width
Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32).
The x9, x18, and x36 configurations include parity bits. The two ports can have different aspect ratios.
Each block RAM can be divided into two completely independent 9 Kb block RAMs that can each be configured to any
aspect ratio from 8K x 1 to 512 x 18, with 256 x 36 supported in simple dual-port mode.
Memory Controller Block
Most XA Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting a single-chip DRAM (either
DDR, DDR2, DDR3, or LPDDR), and supporting access rates of up to 800 Mb/s.
The MCB has dedicated routing to predefined FPGA I/Os. If the MCB is not used, these I/Os are available as general
purpose FPGA I/Os. The memory controller offers a complete multi-port arbitrated interface to the logic inside the XA
Spartan-6 FPGA. Commands can be pushed, and data can be pushed to and pulled from independent built-in FIFOs, using
conventional FIFO control signals. The multi-port memory controller can be configured in many ways. An internal 32-, 64-,
or 128-bit data interface provides a simple and reliable interface to the MCB.
The MCB can be connected to 4-, 8-, or 16-bit external DRAM. The MCB, in many applications, provides a faster DRAM
interface compared to traditional internal data buses, which are wider and are clocked at a lower frequency. The FPGA logic
interface can be flexibly configured irrespective of the physical memory device.
Digital Signal Processing—DSP48A1 Slice
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All XA
Spartan-6 FPGAs have many dedicated, full-custom, low-power DSP slices, combining high speed with small size, while
retaining system design flexibility.
Each DSP48A1 slice consists of a dedicated 18 × 18 bit two’s complement multiplier and a 48-bit accumulator, both capable
of operating at up to 390 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance
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