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參數(shù)資料
| 型號： | XA6SLX9-3CSG324Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 324CSGBGA |
| 標準包裝： | 126 |
| 系列： | Spartan®-6 LX XA |
| LAB/CLB數(shù)： | 715 |
| 邏輯元件/單元數(shù)： | 9152 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 200 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-LFBGA，CSPBGA |
| 供應商設備封裝： | 324-CSPBGA |
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012
Product Specification
4
SLICEL
One quarter (25%) of the XA Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the
memory/shift register function.
SLICEX
One half (50%) of the XA Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except
the arithmetic carry option and the wide multiplexers.
Clock Management
Each XA Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually
or cascaded.
DCM
The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270° (CLK0, CLK90, CLK180, and
CLK270). It also provides a doubled frequency CLK2X and its complement CLK2X180. The CLKDV output provides a
fractional clock frequency that can be phase-aligned to CLK0. The fraction is programmable as every integer from 2 to 16,
as well as 1.5, 2.5, 3.5 . . . 7.5. CLKIN can optionally be divided by 2. The DCM can be a zero-delay clock buffer when a clock
signal drives CLKIN, while the CLK0 output is fed back to the CLKFB input.
Frequency Synthesis
Independent of the basic DCM functionality, the frequency synthesis outputs CLKFX and CLKFX180 can be programmed to
generate any output frequency that is the DCM input frequency (FIN) multiplied by M and simultaneously divided by D, where
M can be any integer from 2 to 32 and D can be any integer from 1 to 32.
Phase Shifting
With CLK0 connected to CLKFB, all nine CLK outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, and CLKFX180) can be shifted by a common amount, defined as any integer multiple of a fixed delay. A fixed DCM
delay value (fraction of the input period) can be established by configuration and can also be incremented or decremented
dynamically.
Spread-Spectrum Clocking
The DCM can accept and track typical spread-spectrum clock inputs, provided they abide by the input clock specifications
listed in the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. XA Spartan-6 FPGAs can generate a spread-
spectrum clock source from a standard fixed-frequency oscillator.
PLL
The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in
conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of
400 MHz to 1,080 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O)
adapt the VCO to the required application.
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO
output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the
VCO within its controllable frequency range.
The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive
one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).
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