參數(shù)資料
型號: XA3S200A-4FTG256I
廠商: Xilinx Inc
文件頁數(shù): 40/57頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 200K 256-FBGA
產(chǎn)品培訓模塊: Extended Spartan 3A FPGA Family
標準包裝: 90
系列: Spartan®-3A XA
LAB/CLB數(shù): 448
邏輯元件/單元數(shù): 4032
RAM 位總計: 294912
輸入/輸出數(shù): 195
門數(shù): 200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
45
Miscellaneous DCM Timing
DNA Port Timing
Table 41: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
seconds
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
N/A
minutes
Notes:
1.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2.
This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
3.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
Table 42: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
0.5
1.5
ns
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKH
CLK High time
1.0
ns
TDNACLKL
CLK Low time
1.0
ns
Notes:
1.
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 s.
相關(guān)PDF資料
PDF描述
5746881-2 SCREW RETAINR KIT LO-PRO 4-40UNC
XA6SLX16-3FTG256I IC FPGA SPARTAN 6 14K 256FTGBGA
3-747580-1 CONN FERRULE STEPPED DB37/50
XA6SLX16-3CSG225I IC FPGA SPARTAN 6 14K 225CSGBGA
XA3S500E-4PQG208I IC FPGA SPARTAN-3E 500K 208-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XA3S200A-4FTG256Q 功能描述:IC FPGA SPARTAN-3A 200K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-3A XA 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)
XA3S250E 制造商:XILINX 制造商全稱:XILINX 功能描述:XA Spartan-3E Automotive FPGA Family Data Sheet
XA3S250E-4CPG132I 功能描述:IC FPGA SPARTAN-3E 250K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-3E XA 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)
XA3S250E-4CPG132Q 功能描述:IC FPGA SPARTAN-3E 250K 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-3E XA 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)
XA3S250E-4FT256I 功能描述:IC FPGA SPARTAN-3E 256FPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-3E XA 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)