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參數(shù)資料
| 型號(hào)： | XA-G49 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XA 16-bit microcontroller family 64K FLASH/2K RAM, watchdog, 2 UARTs |
| 中文描述： | 的XA 16位微控制器系列64K的FLASH/2K內(nèi)存，看門狗，2個(gè)UART |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 299K |
| 代理商： | XA-G49 |
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Philips Semiconductors
Preliminary specification
XA-G49
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
2000 Apr 03
35
5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case,
and in most applications this parameter is not used.
6. Please note that the XA-G49 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles.
7. Applies only to an external clock source, not when a crystal or ceramic resonator is connected to the XTAL1 and XTAL2 pins.
t
PXIZ
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
A0 or A1–A3, A12–19
t
AVLL
t
PXIX
t
LLAX
INSTR IN
*
t
LHLL
t
PLPH
t
LLPL
t
AVIVA
SU01073
t
PLIV
A4–A11 or A4–A19
t
IXUA
*
INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
Figure 20. External Program Memory Read Cycle (ALE Cycle)
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
A0 or A1–A3, A12–19
INSTR IN
*
SU00707
A4–A11 or A4–A19
t
AVIVB
*
INSTR IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
A0 or A1–A3, A12–19
Figure 21. External Program Memory Read Cycle (Non-ALE Cycle)
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