參數(shù)資料
型號: X98024L128-3.3-Z
廠商: INTERSIL CORP
元件分類: 消費家電
英文描述: 240MHz Triple Video Digitizer with Digital PLL
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: 14 X 20 MM, ROHS COMPLIANT, MS-022, MQFP-128
文件頁數(shù): 7/29頁
文件大?。?/td> 295K
代理商: X98024L128-3.3-Z
7
FN8220.0
June 6, 2005
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +10.5)*t
PIXEL
D
1
D
3
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P
/G
P
/B
P
[7:0]
HS
OUT
P
10
P
11
P
12
D
2
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
R
S
/G
S
/B
S
[7:0]
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
HSYNC
FIGURE 5. 48 BIT OUTPUT MODE
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
P
10
P
11
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
HSYNC
IN
D
0
R
P
/G
P
/B
P
[7:0]
D
2
D
1
R
S
/G
S
/B
S
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING
X98024
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