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參數(shù)資料
| 型號(hào)： | X98024L128-3.3-Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VID DIGITIZER 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 660 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 監(jiān)控器，電視 |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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24
FN8220.3
March 8, 2006
.
Initialization
The X98024 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
Register 0x23 should be set to 0x78 to enable the DC
Restore function
Reset
The X98024 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HSOUT may sporadically lock to the wrong edge
of HSYNCIN. This will cause the HSOUT to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNCIN signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
HSYNC
IN
(to A and B)
PIXELCLK (A)
(Internal)
DATA
PRI (A)
HS
OUT (A)
DPLL Lock Edge
PIXELCLK = DATACLK Delay
CLKINV
IN (A) = GNDD
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3 PN-2
P
N-1
P
N
Analog Video In
(to A and B)
DATA
SEC (A)
DATACLK (A)
D
0
D
2
D
N-3
D
N-1
CLKINV
IN (B) = GNDD
D
1
D
3
D
N-2
D
N
PIXELCLK (B)
(Internal)
DATA
PRI (B)
HS
OUT (B)
DATA
SEC (B)
DATACLK (B)
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
X98024
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| X98027L128-3.3-Z | 功能描述:IC TRPL VID DIGITIZER 128MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| X-98-499 | 制造商:Brady Corporation 功能描述:Labels External Width:1" |
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