參數(shù)資料
型號(hào)： X98021L128-3.3
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： 210MHz Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 X 20 MM, MS-022, MQFP-128
文件頁(yè)數(shù)： 14/29頁(yè)
文件大小： 294K
代理商： X98021L128-3.3
14
FN8219.0
June 2, 2005
0x17
ABLC Configuration (0x40)
0
ABLC disable
0: ABLC enabled (default)
1: ABLC disabled
1
Reserved
Set to 0.
3:2
ABLC pixel width
Number of black pixels averaged every line for ABLC
function
00: 16 pixels [default]
01: 32 pixels
10: 64 pixels
11: 128 pixels
6:4
ABLC bandwidth
ABLC Time constant (lines) = 2
(5+[6:4])
000 = 32 lines
100 = 256 lines (default)
111 = 4096 lines
7
Reserved
Set to 0.
0x18
Output Format (0x00)
0
Bus Width
0: 24 bits: Data output on R
P
, G
P
, B
P
only; R
S
, G
S
, B
S
are all
driven low (default)
1: 48 bits: Data output on R
P
, G
P
, B
P
, R
S
, G
S
, B
S
1
Interleaving
(48 bit mode only)
0: No interleaving: data changes on same edge of DATACLK
(default)
1: Interleaved: Secondary databus data changes on
opposite edge of DATACLK from primary databus
2
Bus Swap
(48 bit mode only)
0: First data byte after trailing edge of HSOUT appears on
R
P
, G
P
, B
P
(default)
1: First data byte after trailing edge of HSOUT appears on
R
S
, G
S
, B
S
(primary and secondary busses are reversed)
3
Reserved
Set to 0.
4
422
(24 bit mode only)
0: Data is formatted as 4:4:4 (RGB, default)
1: Data is decimated to 4:2:2 (YUV), blue channel is driven
low
5
DATACLK
Polarity
0: HS
OUT
, VS
OUT
, and Pixel Data change on falling edge of
DATACLK (default)
1: HS
OUT
, VS
OUT
, and Pixel Data change on rising edge of
DATACLK
6
VSOUT Polarity
0: Active High (default)
1: Active Low
7
HSOUT Polarity
0: Active High (default)
1: Active Low
0x19
HSOUT Width (0x10)
7:0
HSOUT Width
HSOUT width, in pixels. Minimum value is 0x01 for 24 bit
modes, 0x02 for 48 bit modes.
0x1A
Output Signal Disable (0x00)
0
Three-state R
P
[7:0]
0 = Output byte enabled
1 = Output byte three-stated
These bits override all other I/O settings
Output data pins have 58k
Ω
pulldown resistors to GND
D
.
1
Three-state R
S
[7:0]
2
Three-state G
P
[7:0]
3
Three-state G
S
[7:0]
4
Three-state B
P
[7:0]
5
Three-state B
S
[7:0]
6
Three-state
DATACLK
0 = DATACLK enabled
1 = DATACLK three-stated
7
Three-state
DATACLK
0 = DATACLK enabled
1 = DATACLK three-stated
Register Listing
(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(s)
FUNCTION NAME
DESCRIPTION
X98021
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