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參數(shù)資料
| 型號(hào)： | X98021 |
| 廠商： | Intersil Corporation |
| 英文描述： | 210MHz Triple Video Digitizer with Digital PLL |
| 中文描述： | 210MHz的三路視頻數(shù)字化與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 294K |
| 代理商： | X98021 |
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23
FN8219.0
June 2, 2005
Crystal Oscillator
An external 23MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
EMI Considerations
There are two possible sources of EMI on the X98021:
Crystal oscillator.
The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low
voltage sine wave oscillator circuit, instead of the typical
high-gain square wave inverter-type oscillator, so there
are no harmonics.
The crystal oscillator is not a significant
source of EMI.
Digital output switching.
This is the largest potential
source of EMI. However, the EMI is determined by the
PCB+ layout and the loading on the databus. The way to
control this is to put series resistors on the output of all the
digital pins. These resistor values should be adjusted to
optimize signal quality on the bus. Intersil recommends
starting with 22
Ω
and adjusting as necessary for the
particular PCB layout and device loading.
Recommendations for minimizing EMI are:
Minimize the databus trace length
Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of
the digital output series resistors to reduce slew rates on the
bus. This can only be done as long as the scaler’s setup and
hold timing requirements continue to be met.
Alternate Pixel Sampling
Two X98021s (AFE
A
and AFE
B
) may be used
simultaneously to achieve effective sample rates greater
than 210MHz. Each AFE is programmed with an HTOTAL
value equal to one-half of the total number of pixels in a line.
The CLOCKINV
IN
pin for AFE
A
is tied to ground, AFE
B
is
tied to V
D
. Both AFEs are otherwise programmed identically,
though some minor phase adjustment may be needed to
compensate for any propagation delay mismatch between
the two AFEs.
The CLOCKINV
IN
setting shifts the phase of AFE
B
by 180
degrees from AFE
A
. AFE
A
now samples the even pixels on
the rising edge of its DATACLK, while AFE
B
samples the odd
pixels on the rising edge of its clock. With each AFE in 24 bit
mode, two 24 bit data streams are generated (Figure 9).
With both AFEs configured for 48 bit mode, a 96 bit
datastream is generated (Figure 10).
In both cases, AFE
A
and AFE
B
are on different DATACLK
domains. In 24 bit mode, the data from each AFE must be
latched on the rising edge of that AFE’s DATACLK. In 48 bit
mode, the frequencies are low enough that the rising edge of
AFE B can be used to capture both AFE
B
and AFE
A
data.
HSYNC
IN
(to A and B)
DATACLK (A)
DATA (A)
HS
OUT
(A)
DATACLK (B)
DATA (B)
HS
OUT
(B)
DPLL Lock Edge
DATACLK Delay
CLKINV
IN
(A) = GND
D
CLKINV
IN
(B) = V
D
D
0
D
2
D
3
D
N
D
1
D
N-3
D
N-1
D
N-2
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3
P
N-2
P
N-1
P
N
Analog Video In
(to A and B)
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
X98021
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X98021L128-3.3 | 210MHz Triple Video Digitizer with Digital PLL |
| X98021L128-3.3-Z | 210MHz Triple Video Digitizer with Digital PLL |
| X98024 | 240MHz Triple Video Digitizer with Digital PLL |
| X98024L128-3.3 | 240MHz Triple Video Digitizer with Digital PLL |
| X98024L128-3.3-Z | 240MHz Triple Video Digitizer with Digital PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X98021_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
| X98021EVAL | 制造商:Intersil Corporation 功能描述:EVALUATION BOARD FOR X98021 - Bulk |
| X98021L128-3.3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:210MHz Triple Video Digitizer with Digital PLL |
| X98021L128-3.3-Z | 功能描述:IC TRPL VID DIGITIZER 128MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| X98024 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:240MHz Triple Video Digitizer with Digital PLL |
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