參數(shù)資料
型號: X98017
廠商: Intersil Corporation
英文描述: 170MHz Triple Video Digitizer with Digital PLL
中文描述: 170MHz的三路視頻數(shù)字化與數(shù)字鎖相環(huán)
文件頁數(shù): 5/29頁
文件大小: 295K
代理商: X98017
5
FN8218.0
June 6, 2005
t
SETUP
DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
1.3
ns
t
HOLD
DATA valid after rising edge of DATACLK
15pF DATACLK load, 15pF DATA load
(Note 1)
2.0
ns
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
f
SCL
SCL Clock Frequency
0
400
kHz
Maximum width of a glitch on SCL that will
be suppressed
2 XTAL periods min
80
ns
t
AA
SCL LOW to SDA Data Out Valid
5 XTAL periods plus SDA’s RC time
constant
See
comment
μs
t
BUF
Time the bus must be free before a new
transmission can start
1.3
μs
t
LOW
Clock LOW Time
1.3
μs
t
HIGH
Clock HIGH Time
0.6
μs
t
SU:STA
Start Condition Setup Time
0.6
μs
t
HD:STA
Start Condition Hold Time
0.6
μs
t
SU:DAT
Data In Setup Time
100
ns
t
HD:DAT
Data In Hold Time
0
ns
t
SU:STO
Stop Condition Setup Time
0.6
μs
t
DH
Data Output Hold Time
4 XTAL periods min
160
ns
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
Electrical Specifications
Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 170MHz, f
XTAL
= 25MHz, T
A
= 25°C,
unless otherwise noted
(Continued)
SYMBOL
PARAMETER
COMMENT
MIN
TYP
MAX
UNIT
t
SU:STO
t
DH
t
HIGH
t
SU:ST
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
FIGURE 1. 2 WIRE INTERFACE TIMING
DATACLK
t
SETUP
t
HOLD
DATACLK
Pixel Data
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
X98017
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