- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376449 > X98014 (Intersil Corporation) 140MHz Triple Video Digitizer with Digital DLL(帶有數(shù)字PLL的140MHz三路視頻信號數(shù)字轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | X98014 |
| 廠商： | Intersil Corporation |
| 英文描述： | 140MHz Triple Video Digitizer with Digital DLL(帶有數(shù)字PLL的140MHz三路視頻信號數(shù)字轉(zhuǎn)換器) |
| 中文描述： | 140MHz的三路視頻數(shù)字化與數(shù)字DLL（帶有數(shù)字鎖相環(huán)的140MHz的三路視頻信號數(shù)字轉(zhuǎn)換器） |
| 文件頁數(shù)： | 24/29頁 |
| 文件大小： | 444K |
| 代理商： | X98014 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁
24
FN8217.3
March 8, 2006
.
Initialization
The X98014 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
Register 0x23 should be set to 0x78 to enable the DC
Restore function
Reset
The X98014 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HS
OUT
may sporadically lock to the wrong edge
of HSYNC
IN
. This will cause the HS
OUT
to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNC
IN
signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
HSYNC
IN
(to A and B)
PIXELCLK (A)
(Internal)
DATA
PRI
(A)
HS
OUT
(A)
DPLL Lock Edge
PIXELCLK = DATACLK Delay
CLKINV
IN
(A) = GND
D
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3
P
N-2
P
N-1
P
N
Analog Video In
(to A and B)
DATA
SEC
(A)
DATACLK (A)
D
0
D
2
D
N-3
D
N-1
CLKINV
IN
(B) = GND
D
D
1
D
3
D
N-2
D
N
PIXELCLK (B)
(Internal)
DATA
PRI
(B)
HS
OUT
(B)
DATA
SEC
(B)
DATACLK (B)
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
X98014
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X98017 | 170MHz Triple Video Digitizer with Digital PLL |
| X98017L128-3.3 | GIGATRUE 550 CAT PATCH CABLE NO BOOT 20FT BLACK |
| X98017L128-3.3-Z | GIGATRUE 550 CAT PATCH CBL NO BOOT 20FT BK 25 PK |
| X98021 | 210MHz Triple Video Digitizer with Digital PLL |
| X98021L128-3.3 | 210MHz Triple Video Digitizer with Digital PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X98014_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:140MHz Triple Video Digitizer with Digital PLL |
| X98014L128-3.3 | 制造商:Intersil Corporation 功能描述:140MHz Triple Video Digitizer with Digital DLL |
| X98014L128-3.3-Z | 功能描述:IC VIDEO DIGITIZER TRPL 128MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| X98017 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:170MHz Triple Video Digitizer with Digital PLL |
| X98017_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:170MHz Triple Video Digitizer with Digital PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。