參數(shù)資料
型號: X9525V20I
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules
中文描述: DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 5/26頁
文件大小: 578K
代理商: X9525V20I
5
FN8210.0
March 10, 2005
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9525
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL-
EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera-
tion. (Refer to Figure 5.).
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9525 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
Hx
and R
Lx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R
w
x
) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9525, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The intial values of the
DCP WCR’s (before the contents of the NVM is loaded
into the WCR) are 0 and 255 for DCP1 (100 tap) and
DCP2 (256 tap) respectively. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
ACK
returned
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 5.
Acknowledge Polling Sequence
DECODER
RESISTOR
ARRAY
R
Hx
FET
SWITCHES
R
Lx
R
Wx
0
1
2
N
WIPER
COUNTER
REGISTER
(WCR)
NON
MEMORY
(NVM)
VOLATILE
“WIPER”
Figure 6.
DCP Internal Structure
X9525
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