參數(shù)資料
型號: X9525V20I
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules
中文描述: DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 1/26頁
文件大?。?/td> 578K
代理商: X9525V20I
1
FN8210.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
Intersil (and design) is a registered trademark of Intersil Americas Inc.
2001 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PRELIMINARY
X9525
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Dual DCP, EEPROM Memory
FEATURES
Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10k
—256 Tap - 50k
—Non-Volatile
—Write Protect Function
2kbit EEPROM Memory with Write Protect & Block
Lock
TM
Device ID Addressability
2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter
(GBIC) specification
—Adressable
Single Supply Operation
—2.7V to 5.5V
Hot Pluggable
Packages
—CSP (Chip Scale Package)
—20 Pin TSSOP
DESCRIPTION
The X9525 combines two Digitally Controlled Potentiom-
eters (DCP’s), and integrated EEPROM with Block
Lock protection. All functions of the X9525 are
accessed by an industry standard 2-Wire serial interface.
The DCP’s of the X9525 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9525 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi-
gabit Interface Converter (GBIC) specification. The inte-
gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
BLOCK DIAGRAM
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
SDA
SCL
CONSTAT
REGISTER
PROTECT
LOGIC
EEPROM
ARRAY
THRESHOLD
RESET LOGIC
4
2kbit
8
R
H1
R
W1
R
L1
R
H2
R
W2
R
L2
WP
8 - BIT
Ao
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
Data Sheet
March 10, 2005
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