參數(shù)資料
型號: X9523V20I-A
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Laser Diode Control for Fiber Optic Modules
中文描述: DIGITAL POTENTIOMETER, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 22/30頁
文件大?。?/td> 509K
代理商: X9523V20I-A
22
FN8209.0
March 10, 2005
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
A.C. TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
CAPACITANCE (T
A
= 25°C, F = 1.0 MHZ, V
CC
= 5V)
Notes: 1. Typical values are for T
A
= 25°C and V
CC
= 5.0V
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Symbol
f
SCL
t
IN(5)
t
AA(5)
t
BUF(5)
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH(5)
t
R (5)
t
F (5)
t
SU:WP
t
HD:WP
Cb
(5)
Parameter
400kHz
Min
Max
Units
SCL Clock Frequency
0
400
kHz
Pulse width Suppression Time at inputs
50
ns
SCL LOW to SDA Data Out Valid
0.1
0.9
μ
s
Time the bus free before start of new transmission
1.3
μ
s
Clock LOW Time
1.3
μ
s
Clock HIGH Time
0.6
μ
s
Start Condition Setup Time
0.6
μ
s
Start Condition Hold Time
0.6
μ
s
Data In Setup Time
100
ns
Data In Hold Time
0
μ
s
Stop Condition Setup Time
0.6
μ
s
Data Output Hold Time
50
ns
SDA and SCL Rise Time
20 +.1Cb
(2)
300
ns
SDA and SCL Fall Time
20 +.1Cb
(2)
300
ns
WP Setup Time
0.6
μ
s
WP Hold Time
0
μ
s
Capacitive load for each bus line
400
pF
Input Pulse Levels
0.1V
CC
to 0.9V
CC
10ns
0.5V
CC
See Figure 20
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
t
WC(4)
Nonvolatile Write Cycle Time
5
10
ms
Symbol
Parameter
Max
Units
Test Conditions
C
OUT
(5)
Output Capacitance (SDA, V1RO, V2RO, V3RO)
8
pF
V
OUT
= 0V
C
IN
(5)
Input Capacitance (SCL, WP, MR)
6
pF
V
IN
= 0V
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