參數(shù)資料
型號(hào): X9523V20I-A
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計(jì)
英文描述: Laser Diode Control for Fiber Optic Modules
中文描述: DIGITAL POTENTIOMETER, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁數(shù): 2/30頁
文件大?。?/td> 509K
代理商: X9523V20I-A
2
FN8209.0
March 10, 2005
DETAILED DEVICE DESCRIPTION
The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset
control, V1/Vcc low voltage reset control, and two sup-
plementary voltage monitors in one package. These
functions are suited to the control, support, and monitor-
ing of various system parameters in fiber optic modules.
The combination of the X9523 fucntionality lowers sys-
tem cost, increases reliability, and reduces board space
requirements using Intersil’s unique XBGA packaging.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V
CC
activates the Power-on Reset
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V
CC
falls below the mini-
mum V
CC
trip point. V1RO remains HIGH until V
CC
returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out-
put (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two moni-
tor outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip volt-
ages to be individually programmed with high accu-
racy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.
The device features a 2-Wire interface and software
protocol allowing operation on an I
2
C compatible
serial bus.
PIN CONFIGURATION
V2
NC
R
L2
V3
NC
R
H1
3
4
5
V1 / Vcc
V1RO
SCL
SDA
NC
R
W1
R
L1
7
8
9
V
SS
10
R
H2
R
W2
1
2
18
17
19
20
14
13
12
11
15
16
MR
WP
6
V3RO
V2RO
NOT TO SCALE
XBGA
20 Pin TSSOP
2
3
4
A
B
C
D
E
Top View – Bumps Down
1
R
L2
R
W2
R
H2
V2
WP
V3RO
SCL
NC
SDA
R
L1
V2RO
V1 / Vcc
V3
V1RO
NC
NC
R
H1
MR
V
SS
R
W1
X9523
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