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參數(shù)資料
| 型號： | X9470V24I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | RF Power Amplifier (PA) Bias Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 2/25頁 |
| 文件大小： | 542K |
| 代理商： | X9470V24I |
PeimnayInomaion
18
V
System (Digital) Supply Voltage
19
V
CC
System (Digital) Supply Voltage
20
V +
Positive voltage supply for the instrumentation amplifier and other analog circuits.
21
V
OUT
Instrumentation Amplifier output that is 20x or 50x the voltage across the Rsense pins.
22
INC/DEC
Status output that indicates the state of the comparator. When this pin is HIGH, the RBIAS potentiometer will in-
crement; when the pin is LOW, the RBIAS potentiometer will decrement. This pin is open drain and requires ex-
ternal resistor pull-up.
23
SHDN
Shutdown the output op amp. When SHDN is active (HIGH), the V
24
V
SENSE-
Negative sense voltage Input terminal
2 of 25
REV 11.16 3/20/03
www.xicor.com
Preliminary Information
X9470
PIN CONFIGURATION
ORDERING INFORMATION
PIN DESCRIPTIONS
Part Number
Temperature Range
Package
X9470V24I
-40°C TO 85°C
24-Lead TSSOP
TSSOP pin
1
2
Symbol
V
SENSE+
RH
REF
Brief Description
Positive sense voltage input terminal
Upper Terminal of Potentiometer, called the R
upper voltage limit of the adjustment for the Up/Down threshold of the comparator.
Lower Terminal of Potentiometer, called the R
lower voltage limit of the adjustment for the Up/Down threshold of the comparator.
Wiper Terminal of Potentiometer, called the R
the Up/Down comparator. Also referred to as the V
Analog ground to allow single point grounding external to the package to minimize digital noise.
System (Digital) Ground Reference
Chip Select. This input enables bias calibration adjustments to the R
pull-down.
Dual function. Function 1: The increment control input. Increments or decrements the R
Function 2: Serial Data Clock Input. Requires external pull-up.
Serial Data Input. Bi-directional 2-wire interface. Requires external pull-up.
Upper Terminal of Potentiometer, called the R
BIAS
upper limit of the bias voltage to the PA (or V
BIAS
Wiper Terminal of Potentiometer, called the R
BIAS
voltage that will appear at the V
BIAS
pin.
Lower Terminal of Potentiometer, called the R
BIAS
lower limit of the bias voltage to the PA (or V
BIAS
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
System (Digital) Ground Reference
This is the bias output voltage pin and is used to drive the filter network to the PA gate.
REF
potentiometer. The voltage applied to this pin will determine the
3
RL
REF
REF
potentiometer. The voltage applied to this pin will determine the
4
RW
REF
REF
potentiometer. The voltage on this pin will be the threshold for
REF
of the comparator.
5
6
7
AGND
VSS
CS
BIAS
potentiometer. CMOS input with internal
8
SCL
BIAS
potentiometer.
9
SDA
RH
10
BIAS
potentiometer. The voltage applied to this pin will determine the
pin).
potentiometer. This voltage is the equivalent to the unbuffered
11
RW
BIAS
12
RL
BIAS
potentiometer. The voltage applied to this pin will determine the
pin).
13
A0
14
A1
15
A2
16
17
VSS
V
BIAS
BIAS
pin is pulled LOW.
V
OUT
V+
V
CC
RW
REF
AGND
TSSOP
1
3
4
5
6
7
8
9
10
11
12
14
13
20
19
18
17
16
15
X9470
V
sense+
RL
REF
V
sense-
INC/DEC
VSS
CS
V
CC
V
BIAS
VSS
A2
A1
RH
BIAS
RW
BIAS
SDA
SCL
RL
BIAS
A0
24
22
21
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