參數(shù)資料
型號: X9430WV24I-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Dual Digitally Controlled Potentiometer (XDCP) with Operational Amplifier
中文描述: DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝: PLASTIC, TSSOP-24
文件頁數(shù): 1/21頁
文件大?。?/td> 881K
代理商: X9430WV24I-2.7
REV 1.0 6/20/00
Characteristics subject to change without notice.
1 of 21
www.xicor.com
Preliminary Information
1-888-INTERSIL or www.intersil.com/tsc
Programmable Analog
X9430
Dual Digitally Controlled Potentiometer (XDCP
) with Operational Amplifier
FEATURES
Two CMOS voltage operational amplifiers
Two digitally controlled potentiometers
Can be combined or used separately
Amplifiers
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
Digitally controlled potentiometer
—Dual 64 tap potentiometers
—R
total
= 10k
—SPI serial interface
—V
CC
= 2.7V to 5.5V
DESCRIPTION
The X9430 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers or using them as com-
plete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The SPI serial
port, common to both pots, allows the user to program
the connection of the wiper output to any of the resistor
nodes in the series string. The wiper position is saved
in the on board E2 memory to allow for nonvolatile res-
toration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical appli-
cation is to implement the amplifier as a wiper buffer in
circuits that use the potentiometer as a voltage refer-
ence. The potentiometer can also be combined with
the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
V
OUT1
Control and
Memory
CS
SCK
SO
SI
A1
A0
+
V
CC
V
NI0
V+
V–
R
W0
V
SS
V
OUT0
+
V
NI1
V
INV1
V
INV0
R
H0
R
L0
R
W1
R
L1
R
H1
WCR1
WCR0
WP
HOLD
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
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