參數(shù)資料
型號: X9418YV24Z
廠商: Intersil
文件頁數(shù): 5/20頁
文件大小: 0K
描述: IC XDCP DUAL 64TAP 2.5K 24-TSSOP
標(biāo)準包裝: 62
系列: XDCP™
接片: 64
電阻(歐姆): 2.5k
電路數(shù): 2
溫度系數(shù): 標(biāo)準值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
13
FN8194.3
October 12, 2006
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
AC TIMING (over recommended operating conditions)
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
5V
1533
Ω
100pF
SDA Output
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
Symbol
Parameter
Min.
Max.
Unit
fSCL
Clock frequency
400
kHz
tCYC
Clock cycle time
2500
ns
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT
SDA data input hold time
30
ns
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
tAA
SCL low to SDA data output valid time
900
ns
tDH
SDA data output hold time
50
ns
TI
Noise suppression time constant at SCL and SDA inputs
50
ns
tBUF
Bus free time (prior to any transmission)
1300
ns
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
X9418
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