參數(shù)資料
型號(hào): X9410WV24-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計(jì)
英文描述: Low Noise/Low Power/SPI Bus
中文描述: DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝: 4.40 MM, TSSOP-24
文件頁數(shù): 7/21頁
文件大小: 123K
代理商: X9410WV24-2.7
X9410
Characteristics subject to change without notice.
7 of 21
REV 1.1 10/6/00
www.xicor.com
Figure 8. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction
Instruction Set
I
1
I
0
0
1
Operation
I
3
1
I
2
0
R
1
0
R
0
0
P
1
0
P
0
P
0
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Read the contents of the Wiper Counter Register
pointed to by P
0
Write new value to the Wiper Counter Register
pointed to by P
0
Read the contents of the Data Register pointed to
by P
0
and R
1
–R
0
Write new value to the Data Register pointed to
by P
0
and R
1
–R
0
Transfer the contents of the Data Register pointed
to by R
1
–R
0
to the Wiper Counter Register pointed
to by P
0
Transfer the contents of the Wiper Counter
Register pointed to by P
0
to the Register pointed
to by R
1
–R
0
Transfer the contents of the Data Registers
pointed to by R
1
–R
0
of both pots to their
respective Wiper Counter Register
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R
1
–R
0
of both pots
Enable Increment/decrement of the Wiper
Counter Register pointed to by P
0
Read the status of the internal write cycle, by
checking the WIP bit.
1
0
1
0
0
0
0
P
0
1
0
1
1
R
1
R
0
0
P
0
Write Data Register
1
1
0
0
R
1
R
0
0
P
0
XFR Data Register to
Wiper Counter Register
1
1
0
1
R
1
R
0
0
P
0
XFR Wiper Counter
Register to Data Register
1
1
1
0
R
1
R
0
0
P
0
Global XFR Data Register
to Wiper Counter Register
0
0
0
1
R
1
R
0
0
0
Global XFR Wiper
Counter Register to Data
Register
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
1
0
0
0
R
1
R
0
0
0
0
0
1
0
0
0
0
P
0
0
1
0
1
0
0
0
1
SCK
SI
V
W
/R
W
INC/DEC CMD Issued
t
WRID
Voltage Out
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