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參數(shù)資料
| 型號： | X9252YV24I-2.7 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally-Controlled (XDCP) potentiometer |
| 中文描述： | 四數(shù)字控制（數(shù)字電位器）電位 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 126K |
| 代理商： | X9252YV24I-2.7 |
8 of 21
REV 1.4.1 7/29/03
www.xicor.com
X9252
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Notes:
(1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
W(n)(actual)
)–V(R
W(n)(expected)
)]/MI
V(R
W(n)(expected)
) = n(V(R
H
)-V(R
L
))/255 + V(R
L
), with n from 0 to 255.
(2) Relative linearity is a measure of the error in step size between taps = [V(R
W(n+1)
)–(V(R
W(n)
) + MI)]/MI , with n from 0 to 254
(3) 1 Ml = Minimum Increment = [V(R
H
)–V(R
L
)]/255.
(4) Typical values are for T
A
= 25°C and nominal supply voltage.
(5) This parameter is not 100% tested.
(6) Ratiometric temperature coefficient = (V(R
W
)
T1(n)
–V(R
W
)
T2(n)
)/[V(R
W
)
T1(n)
(T1–T2)] x 10
6
, with T1 & T2 being 2 temperatures, and
n from 0 to 255.
(7) Measured with wiper at tap position 255, R
L
grounded, using test circuit.
(8) t
WC
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time
from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a
valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle.
(9) The recommended power up sequence is to apply V
CC
/V
SS
first, then the potentiometer voltages. During power up, the data sheet
parameters for the DCP do not fully apply until t
D
after V
CC
reaches its final value. In order to prevent unwanted tap position
changes, or an inadvertant store, bring the CS pin high before or concurrently with the V
CC
pin on power up.
Symbol
t
WC
(8)(5)
Parameter
Typ.
5
Max.
10
Units
ms
Non-volatile write cycle time
Symbol
t
WRL
(5)
Parameter
Min.
5
Max.
20
Units
μs
SCL rising edge to wiper code changed, wiper response time after
instruction issued (all load instructions)
Test Circuit
Equivalent Circuit
Force
Current
Test Point
R
W
C
H
C
L
R
W
R
TOTAL
C
W
R
H
R
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9252YV24IZ-2.7 | 功能描述:IC POT DGTL QUAD 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| X9258 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise/Low Power/2-Wire Bus/256 Taps |
| X9258)06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers |
| X9258_11 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers(XDCP?) |
| X9258_13 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise/Low Power/2-Wire Bus/256 Taps |
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