參數(shù)資料
型號(hào)： X9111TV14Z-2.7
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計(jì)
英文描述： Single Digitally-Controlled (XDCP⑩) Potentiometer
中文描述： 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14
封裝： 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 323K
代理商： X9111TV14Z-2.7
5
FN8159.4
September 15, 2006
bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
. The
R/W bit is used to set the device to either read or write
mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
TABLE 3. STATUS REGISTER, SR (1-BIT)
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
WIP
(LSB)
TABLE 3. IDENTIFICATION BYTE FORMAT
ID3
ID2
ID1
ID0
0
A1
A0
R/W
0
1
0
1
(MSB)
(LSB)
Device Type
Identifier
Internal Slave
Address
Read or
Write Bit
TABLE 4. INSTRUCTION BYTE FORMAT
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Instruction
Opcode
Register
Selection
RB
RA
REGISTER
0
0
1
1
0
1
0
1
DR0
DR1
DR2
DR3
X9111
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