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參數(shù)資料
| 型號： | X88C75 SLIC |
| 英文描述： | Port Expander and EE Memory(雙面，可同時讀寫，與通用8051系列直接接口,微控制器外圍芯片) |
| 中文描述： | 端口擴展和EE內(nèi)存（雙面，可同時讀寫，與通用8051系列直接接口，微控制器外圍芯片） |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 240K |
| 代理商： | X88C75 SLIC |
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X88C75 SLIC
E
2
4
Page Write Operation
Toggle Bit Polling
Because the X88C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
determine the early completion of a write cycle. During
the internal programming cycle, I/O
6
will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
Figure 1. Toggle Bit Polling
internal cycle is complete, the toggling will cease and
the device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A
12
during a write must match the state
of A
12
during polling.
tBLC
CE
ALE
A/D0–A/D7
A8–A12
WR
PSEN(RD)
AIN
DIN
A12=n
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
tWC
2887 ILL F04
AIN
DIN
A12=n
AIN
DIN
A12=n
AIN
DIN
A12=n
AIN
DOUT
A12=x
AIN
ADDR
AIN
Next Address
RD
LAST BYTE
WRITTEN
CE
ALE
A/D0–A/D7
A8–A12
WR
AIN
DIN
A12=n
OPERATION
AIN
DOUT
A12=n
AIN DOUT
A12=n
AIN
DOUT
A12=n
AIN
DOUT
A12=x
AIN
ADDR
I/O6=X
X88C75 READY FOR
NEXT OPERATION
2887 ILL F05
I/O6=X
I/O6=X
I/O6=X
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