- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372537 > X88064PI-60 E2 Micro-Peripheral PDF資料下載
參數(shù)資料
| 型號： | X88064PI-60 |
| 英文描述： | E2 Micro-Peripheral |
| 中文描述： | E2微型外設(shè) |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 81K |
| 代理商： | X88064PI-60 |
X88064
2
Software Data Program Cont Pin configuration
memory write management. SDP controls write opera-
tions to the entire memory. When enabled, the host micro-
processor must send a special 3 byte command sequence
before any byte or page writes to unlocked locations in the
memory.
PIN NAMES
PIN NAME
PSEN
I/O
I
DESCRIPTION
Content of E
HIGH. The device then places on the data bus (AD
latched address.
Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
2
memory can be read by lowering the PSEN and holding both RD and WR
0
–AD
7
) the contents of E
2
memory at the
A
8
–A
12
I
AD
0
–AD
7
I/O
Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a
HIGH to LOW transition.
During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is
placed on the bus. The rising edge of
WR
latches data into the device.
WR
I
RD
I
The RD input is active LOW and is used to read content of the E
address. Both PSEN an WR signals must be held HIGH during RD controlled read operation.
WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order
to disable write to the E
memory. Taking WC HIGH prior to t
the last write cycle to the start of internal programming cycle) will inhibit the write operation.
The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE
HIGH to LOW transition in order to generate a valid internal device select signal. Holding this
pin HIGH and ALE LOW will place the device in standby mode.
Address Latch Enable input is used to latch the addresses present on the address lines
A
8
–A
12
and AD
0
–AD
7
into the device. The addresses are latched when ALE transitions from
HIGH to LOW.
2
memory at the latched
WC
I
2
BLC
(100ns, the time delay from
CE
I
ALE
I
7023 FRM F02
NC
A
12
NC
NC
WC
PSEN
A/D
0
A/D
1
A/D
2
A/D
3
A/D
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
WR
ALE
A
8
A
9
A
11
RD
A
10
CE
A/D
7
A/D
6
A/D
5
X88064
DIP/SOIC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X88064S | E2 Micro-Peripheral |
| X88064S-60 | E2 Micro-Peripheral |
| X88064SI | E2 Micro-Peripheral |
| X88064SI-60 | E2 Micro-Peripheral |
| X88C64(中文) | EE Micro-Peripheral(多重地址/數(shù)據(jù)總線，快鎖定，高速CMOS,微控制器外圍芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X88064S | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X88064S-60 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X88064SI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X88064SI-60 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X88257 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。