參數(shù)資料
型號(hào): X88064SI-60
英文描述: E2 Micro-Peripheral
中文描述: E2微型外設(shè)
文件頁數(shù): 1/15頁
文件大?。?/td> 81K
代理商: X88064SI-60
iAPX88/188, MCS
196, MCS51 Compatible*
* All other brand and product names may be trademarks or
registered trademarks of their respective companies.
7023-2.3 1/29/97 T0/C2/D0 SH
Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
64K
X88064
8192 x 8 Bit
E
2
Microcontroller Peripheral
Block Lock Write Control
—Eight 1K Byte Blocks
- Lockable Independently or in Combination
Multiplexed Address/Data Bus
—Direct Interface to Popular Microcontrollers
High Performance CMOS
—Fast Access Times, 60ns and 80 ns
—Low Power
- 30mA Active Maximum
- 150
μ
A Standby Maximum
Software Data Protection
Toggle Bit Polling
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
DESCRIPTION
The X88064 is a high speed byte wide microperipheral
device with eight 1K byte blocks of E
directly connected to industry standard high performance
microprocessors. This peripheral provides two levels of
memory write control, the standard Software Data Pro-
gram (SDP) control and Block Lock.
2
PROM and can be
Block Lock provides a higher level of memory write con-
trol above SDP This allows the software developer to
partition any or all of the eight 1K byte blocks as In-Circuit
Programmable ROM (ICPROM). Once locked, a block of
memory must first be unlocked before being written. Not
even a write operation using the SDP sequence will
change the contents of a locked block. Since a distinct, 6
byte, software command sequence locks and unlocks
the memory, the software developer has complete con-
trol of the memory contents.
CONTROL
LOGIC
INDIVIDUALLY LOCKABLE
D
E
C
O
D
E
R
L
A
T
C
H
A/D
0
–A/D
7
A
8
–A
12
INTERFACE
CONTROL
WR
RD
PSEN
CE
WC
SOFTWARE DATA PROTECT
(SDP)
POWER-ON RESET
AND V
CC
SENSE
WE
OE
BUS TRANSCEIVER
A/D
0
–A/D
7
1Kx8 BLOCKS
ALE
BLOCK LOCK
E
ARRAY
2
PROM
A
PPLICATION
N
OTE
A V A I L A B L E
Application Brief
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