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參數(shù)資料
| 型號： | X79002V20IT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC NV SELECT OUT/MEM 20TSSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | 417k |
12
FN8147.0
March 17, 2005
VOLTAGE REFERENCES
The device includes an on-chip bandgap reference
circuit with 1.21 V nominal output voltage. This voltage is
available at pin VRef as an output.
The voltages at pins VH and VL determine the DAC
output voltage at full scale and zero scale respectively.
Full scale is when the DAC input register is FFF hex (all
ones), and zero scale is when the DAC input register is
000 hex (all zeros).
V(VH) and V(VL) can be generated on-chip and can be
independently programmed to the values indicated in
table 1. VH must always be at a higher voltage than VL.
VH must not be higher than 3.1V. VL & VH can also be
independently disabled, in which case they become
inputs to the device.
SERIAL INTERFACE
Serial Interface Conventions
The device supports the SPI interface hardware protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive
operations. The X79000 operates as a slave in all
applications.
The device is accessed via the SI and SCK pins, while
the output data is presented at the SO pin. Input data at
pin SI is clocked-in on the rising edge of SCK, when CS
and RDY are both LOW. Output data at pin SO is
clocked-out on the falling edge of SCK.
All commands start with a falling edge at the input pin
CS. Write operations end with a rising edge at the input
pin CS after the last bit of the data bytes being written is
clocked-in. Read operations end with a rising edge at the
input pin CS after the last bit of the data byte being read
is clocked-out.
X79000 MEMORY MAP
The X79000 contains a 512-bit array of mixed volatile
and nonvolatile memory. The array is organized as 64
bytes, and it’s logically split up into two parts, namely:
– General Purpose Memory (GPM)
– Control and Status Registers
The GPM is all nonvolatile EEPROM, located at memory
addresses 00h to 37h.
Figure 2. X79000 Memory Map
The Control and Status registers of the X79000 are used
in the test and setup of the device in a system, and
include the DAC volatile register and the DAC nonvolatile
initial value register. These registers are realized as a
combination of both volatile and nonvolatile memory.
These registers reside in the memory locations 38h
through 3Fh. The reserved bits within registers 38h
through 3Dh must be written as “0” if writing to them, and
should be ignored when reading. The reserved registers,
3Ah, 3Bh, 3Eh and 3Fh, must not be written, and their
content should be ignored.
Factory control bit settings:
38h, 39h, 3Fh = All “0”s
3Ch = 1000 0100 (84 hex)
All communication to the X79000 over the SPI bus is
conducted by sending the MSB of each byte of data first.
The memory is physically realized as one contiguous
array, organized as 8 pages of 8 bytes each.
Bit 0
Bit 7
Address
Size
8 Bytes
56 Bytes
00h
37h
38h
3Fh
Control & Status
Registers
General Purpose
Memory (GPM)
...
X79000, X79001, X79002
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