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參數(shù)資料
| 型號(hào)： | X79002V20IT1 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NV SELECT OUT/MEM 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | 417k |
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1
FN8147.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X79000, X79001, X79002
NV DAC with Selectable Output Range
and Memory
FEATURES
12-Bit Resolution
Selectable full scale and zero scale voltages
Optional External full scale and zero scale
references
Programmable, non-volatile DAC initial value
register
Optional UP/DOWN interface
Guaranteed Monotonic Operation, <0.5LSB DNL
Buffered Output Option
Integrated Voltage Reference Option
Voltage Reference Output (1.21V) Option
6 s settling time, full scale
SPI interface, 5MHz
Up to 5 slave Address Pins
Power-up recall and ready output
56 Bytes of general purpose EEPROM
Asynchronous clear pin and control bit
VCC = 5V ±10%
20-lead TSSOP
NV DAC
DESCRIPTION
The X79000 is a family of Single Channel Non-Volatile
(NV)
Digital-to-Analog
Converters
with
integrated
voltage reference, configurable output buffer, general
purpose EEPROM, and selectable full scale and zero
offset voltages.
The X79000 series implements an SPI serial bus
interface with slave address identification allowing up
to 32 devices on some options. The full scale and
zero scale voltages and the DAC initial value register
can be set via the SPI bus interface. Optional pins
are provided for Up/Down style interface allowing for
increment and decrement of the DAC register in 1, 4,
or 16 steps at a time.
A Power-on Recall circuit is implemented to keep the
DAC output at high impedance on power-up and to load
an initial user defined value from non-volatile memory. A
power-up ready signal is provided to alert the system to
begin operations.
Additional general purpose non-volatile memory (56
Bytes) is provided for curve-fit profile setting, signal
conditioning parameters, or device and system
indentification.
X79000 FUNCTIONAL DIAGRAM
Voltage
Reference
Variable Gain
& Level Shift
Variable Gain
& Level Shift
DAC
Core
+
–
Vout
OE
Vbuf
VFB
Power-up
Logic
Serial
Interface
and
Control
Logic
Vref
RDY
A[2:0]
SCK
SO
SI
CS
General
DAC Register
DAC Shift
DAC Initial
Register
Value Register
CLR
UP
DOWN
Purpose
EEPROM
Vcc
Vss
VH VL
Data Sheet
March 17, 2005
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