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參數(shù)資料
| 型號： | X5165 |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 365K |
| 代理商： | X5165 |
4
FN8128.3
June 1, 2006
Block Diagram
Watchdog
Timer Reset
Data
Register
Command
Decode &
Control
Logic
SI
SO
SCK
CS/WDI
V
CC
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Generation
V
TRIP
+
-
RESET/RESET
Reset
Status
Register
Protect Logic
4K Bits
4K Bits
8K Bits
E
Watchdog Transition
Detector
WP
X5163 = RESET
X5165 = RESET
V
CC
Threshold
Reset Logic
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
NAME
FUNCTION
1
1
CS/WDI
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required
Watchdog Input.
A HIGH
to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW
transition within the watchdog time out period results in RESET/RESET going active.
2
2
SO
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
3
6
WP
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “l(fā)ock” the setting
of the Watchdog Timer control and the memory write protect bits.
4
7
V
SS
Ground
5
8
SI
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
9
SCK
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
7
13
RESET/
RESET
Reset Output
.
RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
CC
falls below the minimum V
CC
sense level. It will remain active until V
CC
rises above
the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out
period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power-
up at 1V and remains active for 200ms after the power supply stabilizes.
8
14
V
CC
Supply Voltage
3-5,10-12
NC
No internal connections
X5163, X5165
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| X5165P-4.5A | 功能描述:IC SUPERVISOR CPU 16K EE 8-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
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