- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371259 > X5043V14I-4.5A RTC Module With CPU Supervisor PDF資料下載
參數(shù)資料
| 型號(hào)： | X5043V14I-4.5A |
| 元件分類(lèi)： | CPU監(jiān)測(cè) |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時(shí)鐘模塊CPU監(jiān)控 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 108K |
| 代理商： | X5043V14I-4.5A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
X5043/X5045
Characteristics subject to change without notice.
8 of 20
REV 1.1.2 5/29/01
www.xicor.com
Figure 8. Read EEPROM Array Sequence
0
1
2
3
4
5
6
7
8
9
10
12 13 14 15
16 17
18 19 20 21 22
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
8 Bit Address
7
6
5
3
2
1
0
8
9
th
Bit of Address
Write Memory Array
Prior to any attempt to write data into the memory
array, the “Write Enable” Latch (WEL) must be set by
issuing the WREN instruction (Figure 5). First pull CS
LOW, then clock the WREN instruction into the device
and pull CS HIGH. Then bring CS LOW again and
enter the WRITE instruction followed by the 8-bit
address and then the data to be written. Bit 3 of the
WRITE instruction contains address bit A
8
, which
selects the upper or lower half of the array. If CS does
not go HIGH between WREN and WRITE, the WRITE
instruction is ignored.
The WRITE operation requires at least 16 clocks. CS
must go low and remain low for the duration of the
operation. The host may continue to write up to 16
bytes of data. The only restriction is that the 16 bytes
must reside within the same page. A page address
begins with address [x xxxx 0000] and ends with [x
xxxx 1111]. If the byte address reaches the last byte on
the page and the clock continues, the counter will roll
back to the first address of the page and overwrite any
data that has been previously written.
For the write operation (byte or page write) to be com-
pleted, CS must be brought HIGH after bit 0 of the last
complete data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 9).
While the write is in progress following a status register
or memory array write sequence, the Status Register
may be read to check the WIP bit. WIP is HIGH while
the nonvolatile write is in progress.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X5045 | RTC Module With CPU Supervisor |
| X5045M8I | RTC Module With CPU Supervisor |
| X5045M8I-2.7 | RTC Module With CPU Supervisor |
| X5045M8I-2.7A | RTC Module With CPU Supervisor |
| X5045M8I-4.5A | RTC Module With CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X5043V14IZ | 功能描述:IC CPU SUPERV 4K EEPROM 14-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開(kāi)路漏極或開(kāi)路集電極 復(fù)位:低有效 復(fù)位超時(shí):最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
| X5043V14IZ-2.7 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-2.7A | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-4.5A | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5045 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。