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參數(shù)資料
| 型號(hào)： | X5043V14I-2.7 |
| 元件分類： | CPU監(jiān)測(cè) |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時(shí)鐘模塊CPU監(jiān)控 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | X5043V14I-2.7 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
X5043/X5045
Characteristics subject to change without notice.
7 of 20
REV 1.1.2 5/29/01
www.xicor.com
Table 2. Device Protect Matrix
Figure 6. Read Status Register Sequence
Figure 7. Write Status Register Sequence
WREN CMD
(WEL)
0
x
1
Device Pin
(WP)
x
0
1
Memory Block
Status Register
(BL0, BL1, WD0, WD1)
Protected
Protected
Writable
Protected Area
Protected
Protected
Protected
Unprotected Area
Protected
Protected
Writable
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
15
0
1
2
3
4
5
6
7
8
9
CS
SCK
SI
SO
High Impedance
Instruction
Data Byte
7
6
5
4
3
2
1
0
10 11 12 13 14 15
Read Memory Array
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
8-bit address. Bit 3 of the READ instruction selects the
upper or lower half of the device. After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO line. The data stored in memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached, the address counter rolls over to address
$000 allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
high. Refer to the Read EEPROM Array Sequence
(Figure 8).
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| X5043V14I-2.7A | RTC Module With CPU Supervisor |
| X5043V14I-4.5A | RTC Module With CPU Supervisor |
| X5045 | RTC Module With CPU Supervisor |
| X5045M8I | RTC Module With CPU Supervisor |
| X5045M8I-2.7 | RTC Module With CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X5043V14I-4.5A | 功能描述:IC SUPERVISOR CPU 4K EE 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時(shí):最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5043V14IZ | 功能描述:IC CPU SUPERV 4K EEPROM 14-TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開(kāi)路漏極或開(kāi)路集電極 復(fù)位:低有效 復(fù)位超時(shí):最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
| X5043V14IZ-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-2.7A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-4.5A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
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