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參數(shù)資料
| 型號： | X5043V14I-2.7 |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 108K |
| 代理商： | X5043V14I-2.7 |
X5043/X5045
Characteristics subject to change without notice.
5 of 20
REV 1.1.2 5/29/01
www.xicor.com
Figure 4. V
TRIP
Programming Sequence
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock
array is internally organized as x8 bits. The device fea-
tures a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple four-wire bus.
protection. The
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that
controls the operation of the device. The instruction
code is written to the device via the SI input. There are
two write operations that requires only the instruction
byte. There are two read operations that use the
instruction byte to initiate the output of data. The
remainder of the operations require an instruction byte,
an 8-bit address, then data bytes. All instruction,
address and data bits are clocked by the SCK input. All
instructions (Table 1), addresses and data are trans-
ferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static,
allowing the user to stop the clock and then start it
again to resume operations where left off. CS must be
LOW during the entire operation.
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
(V
CC
= V
CC
–10mV)
RESET pin
goes active
Measured V
TRIP
-Desired V
TRIP
DONE
Execute
Reset V
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Set V
Sequence
New V
CC
Applied
Old V
CC
Applied
- Error
Execute
Reset V
Sequence
Error
≤
-Emax
-Emax < Error < Emax
YES
NO
Error
≥
Emax
Emax = Maximum Desired Error
=
New V
CC
Applied
Old V
CC
Applied
- Error
=
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name
WREN
WRDI
RSDR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 A
8
011
0000 A
8
010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
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| X5043V14I-4.5A | RTC Module With CPU Supervisor |
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| X5045M8I | RTC Module With CPU Supervisor |
| X5045M8I-2.7 | RTC Module With CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X5043V14I-4.5A | 功能描述:IC SUPERVISOR CPU 4K EE 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5043V14IZ | 功能描述:IC CPU SUPERV 4K EEPROM 14-TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:低有效 復位超時:最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
| X5043V14IZ-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-2.7A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
| X5043V14IZ-4.5A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 4K SPI EEPROM |
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