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參數(shù)資料
| 型號： | X4C105V20I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 296K |
| 代理商： | X4C105V20I |
6
FN8124.0
March 18, 2005
The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 7 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be affected.
Figure 7. Page Write Operation
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1 < n < 16)
X4C105
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